# US 12,216,938 B2 · Interworking method external device and storage device

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- Number: US 12,216,938 B2
- Document ID: US12216938B2
- Status: Granted
- Kind: B2
- Application number: 18/328,780
- Filed: 2023-06-05
- Published: 2024-05-30
- Granted: 2025-02-04
- Earliest claimed: 2022-11-24
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: In Jong Jang
- Web page: https://patentgrep.com/patent/US12216938B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present disclosure relates to a memory controller which supports an interworking method for a test between an external device and a storage device, and a host. The memory controller proposed in the present disclosure may include a first interface configured to communicate with an external device, a second interface configured to communicate with a memory, a command queue configured to store commands received from the external device and a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.

## Claims

### Claim 1

A memory controller comprising:
a first interface configured to communicate with an external device;
a second interface configured to communicate with a memory;
a command queue configured to store commands received from the external device; and
a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.

### Claim 2 (depends on 1)

The memory controller of claim 1,
wherein the first interface communicates with the external device by using a message,
and wherein a header of the message includes a mutex flag field and a mutex counter field.

### Claim 3 (depends on 2)

The memory controller of claim 2,
wherein the command queue includes a plurality of sub-command queues,
and wherein the plurality of sub-command queues stores the commands with different priorities.

### Claim 4

A storage device comprising:
a memory device including a non-volatile memory configured to store data; and
a memory controller configured to control the memory device to write or read the data to or from the memory device, receive a command from an external device, suspend performance of a control operation according to the command for a waiting time corresponding to a value of a mutex counter of the command when a mutex flag is activated, and perform the control operation according to the command when the mutex flag is deactivated.

### Claim 5 (depends on 4)

The storage device of claim 4,
wherein the memory controller communicates with the external device by using a message,
and wherein a header of the message includes a mutex flag field and a mutex counter field.

### Claim 6

A system comprising:
a host; and
a memory device including a non-volatile memory configured to store data; and
a memory controller configured to control the memory device, to write or read the data to or from the memory device, receive a command from the host, suspend performance of a control operation according to the command for a waiting time corresponding to a value of a mutex counter of the command when a mutex flag is activated, and perform the control operation according to the command when the mutex flag is deactivated.

### Claim 7 (depends on 6)

The system of claim 6, wherein the memory controller comprises:
a first interface configured to communicate with the host;
a second interface configured to communicate with the memory device;
a command queue configured to store commands received from the host; and
a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.

### Claim 8 (depends on 6)

The system of claim 6,
wherein the host and the memory controller communicate with each other by using a message,
and wherein a header of the message includes a mutex flag field and a mutex counter field.

### Claim 9 (depends on 8)

The system of claim 8, wherein, during a watchdog timer test, the host sets the mutex flag field for a command to be activated, and sets the mutex counter field of the command to have a value that allows the waiting time of the memory controller until transmitting response to the command to be greater than a watchdog time corresponding to a set value of the watchdog timer.

### Claim 10 (depends on 2)

The memory controller of claim 2,
wherein the message is defined based on an UFS Protocol Information Unit (UPIU) of a universal flash storage (UFS) standard.

### Claim 11 (depends on 10)

The memory controller of claim 10,
wherein the mutex flag field and the mutex counter field are defined at a reserved field of the UPIU.

### Claim 12 (depends on 5)

The storage device of claim 5,
wherein the message is defined based on an UFS Protocol Information Unit (UPIU) of a universal flash storage (UFS) standard.

### Claim 13 (depends on 12)

The storage device of claim 12,
wherein the mutex flag field and the mutex counter field are defined at a reserved field of the UPIU.

### Claim 14 (depends on 8)

The system of claim 8,
wherein the message is defined based on an UFS Protocol Information Unit (UPIU) of a universal flash storage (UPS) standard.

### Claim 15 (depends on 14)

The system of claim 14,
wherein the mutex flag field and the mutex counter field are defined at a reserved field of the UPIU.