# US 12,216,932 B2 · Precise longitudinal monitoring of memory operations

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- Number: US 12,216,932 B2
- Document ID: US12216932B2
- Status: Granted
- Kind: B2
- Application number: 18/327,474
- Filed: 2023-06-01
- Published: 2023-09-28
- Granted: 2025-02-04
- Earliest claimed: 2018-11-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ahmad Yasin; Michael Chynoweth; Rajshree Chabukswar; Muhammad Taher
- Web page: https://patentgrep.com/patent/US12216932B2

## CPC

- G06F 3/0656: {Data buffering arrangements}
- G06F 11/3017: {where the computing system is implementing multitasking (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0673: {Single storage device}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 11/3419: {by assessing time}
- G06F 11/3466: {Performance evaluation by tracing or monitoring}
- G06F 2201/88: Monitoring involving counting
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

## Claims

### Claim 1

An apparatus comprising:
a memory subsystem including a data cache, the memory subsystem to process a load operation; and
load latency hardware including a latency counter, the load latency hardware to record performance monitoring information including an access address associated with the load operation, a data block indicator to indicate whether the load operation was blocked since its data could not be forwarded from a preceding store, and an address block indicator to indicate whether the load operation was blocked due to a potential address conflict with a preceding store.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the performance monitoring information also includes an instruction access latency associated with the load operation.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the performance monitoring information also includes a cache access latency associated with the load operation.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the load operation is to be randomly selected.

### Claim 5

A method comprising:
processing, by a memory subsystem of a hardware processor, the memory subsystem including a data cache, a load operation;
recording, by load latency hardware of the processor, the load latency hardware including a latency counter, performance monitoring information including an access address associated with the load operation, a data block indicator to indicate whether the load operation was blocked since its data could not be forwarded from a preceding store, and an address block indicator to indicate whether the load operation was blocked due to a potential address conflict with a preceding store.

### Claim 6 (depends on 5)

The method of claim 5, wherein the performance monitoring information also includes an instruction access latency associated with the load operation.

### Claim 7 (depends on 5)

The method of claim 5, wherein the performance monitoring information also includes a cache access latency associated with the load operation.

### Claim 8 (depends on 5)

The method of claim 5, further comprising randomly selecting the load operation.

### Claim 9

A system comprising:
a memory; and
a processor including:
a memory subsystem including a data cache, the memory subsystem to process a load operation; and
load latency hardware including a latency counter, the load latency hardware to record performance monitoring information including an access address associated with the load operation, a data block indicator to indicate whether the load operation was blocked since its data could not be forwarded from a preceding store, and an address block indicator to indicate whether the load operation was blocked due to a potential address conflict with a preceding store.

### Claim 10 (depends on 9)

The system of claim 9, wherein the performance monitoring information also includes an instruction access latency associated with the load operation.

### Claim 11 (depends on 9)

The system of claim 9, wherein the performance monitoring information also includes a cache access latency associated with the load operation.

### Claim 12 (depends on 9)

The system of claim 9, wherein the load operation is to be randomly selected.