# US 12,216,925 B2 · Memory control apparatus, method for controlling memory control apparatus, and storage medium > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,925 B2 - Document ID: US12216925B2 - Status: Granted - Kind: B2 - Application number: 18/171,853 - Filed: 2023-02-21 - Published: 2023-08-24 - Granted: 2025-02-04 - Earliest claimed: 2022-02-24 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Wataru Ochiai - Web page: https://patentgrep.com/patent/US12216925B2 ## CPC - G06F 3/0625: {Power saving in storage systems} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0673: {Single storage device} - G11C 7/1093: {Input synchronization} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 2207/2227: Standby or low power modes - G11C 2207/2272: Latency related aspects - G11C 2207/2281: Timing of a read operation - G11C 2207/229: Timing of a write operation - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, includes an output unit configured to change an output mode of the clock signal for data transfer based on a memory access state and to output the clock signal for data transfer to the memory based on the output mode. ## Claims ### Claim 1 A memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, and the memory control apparatus comprising: an output unit configured to change an output mode of the clock signal for data transfer based on a memory access state and to output the clock signal for data transfer to the memory based on the output mode, wherein in a busy state as the memory access state, the output unit sets a first output mode, and constantly outputs the clock signal for data transfer to the memory in the first output mode, and wherein in a non-busy state as the memory access state, the output unit sets a second output mode, and outputs the clock signal for data transfer to the memory as needed in the second output mode. ### Claim 2 (depends on 1) The memory control apparatus according to claim 1, wherein with an effective bandwidth of the memory during a predefined period being greater than or equal to a first threshold value, the memory access state is the busy state, and with the effective bandwidth of the memory during a predefined period being smaller than the first threshold value, the memory access state is the non-busy state. ### Claim 3 (depends on 1) The memory control apparatus according to claim 1, further comprising an issuing unit configured to issue a read or write command to the memory. ### Claim 4 (depends on 3) The memory control apparatus according to claim 3, wherein with a total number of read and write commands issued by the issuing unit during a predefined period being greater than or equal to a second threshold value, the memory access state is the busy state, and with the total number of the read and write commands issued by the issuing unit during a predefined period being smaller than the second threshold value, the memory access state is the non-busy state. ### Claim 5 (depends on 3) The memory control apparatus according to claim 3, wherein the issuing unit issues a synchronization command for synchronizing the clock signal for command transfer and the clock signal for data transfer with each other to the memory. ### Claim 6 (depends on 5) The memory control apparatus according to claim 5, wherein in the busy state as the memory access state, the output unit sets the first output mode, and constantly outputs the clock signal for data transfer to the memory in the first output mode, and wherein in the non-busy state as the memory access state, the output unit sets the second output mode, and outputs the clock signal for data transfer to the memory as needed in the second output mode, wherein in the first output mode, the issuing unit does not issue the synchronization command for synchronizing the clock signal for command transfer and the clock signal for data transfer with each other between issuance of a previous read or write command and issuance of a current read or write command, and wherein in the second output mode, the issuing unit issues the synchronization command for synchronizing the clock signal for command transfer and the clock signal for data transfer with each other between the issuance of the previous read or write command and the issuance of the current read or write command. ### Claim 7 (depends on 6) The memory control apparatus according to claim 6, wherein in the second output mode, the issuing unit issues the previous read or write command to a first rank of the memory, issues the current read or write command to the first rank of the memory, and issues the synchronization command to the first rank of the memory. ### Claim 8 (depends on 6) The memory control apparatus according to claim 6, wherein in the second output mode, the issuing unit issues the previous read or write command to a first rank of the memory, issues the current read or write command to a second rank of the memory, and issues the synchronization command to the second rank of the memory, the second rank being different from the first rank. ### Claim 9 (depends on 1) The memory control apparatus according to claim 1, further comprising a holding unit configured to hold a received access command. ### Claim 10 (depends on 9) The memory control apparatus according to claim 9, further comprising an issuing unit configured to issue a read or write command to the memory based on the access command held by the holding unit. ### Claim 11 (depends on 9) The memory control apparatus according to claim 9, wherein with a number of access commands held by the holding unit being greater than or equal to a third threshold value, the memory access state is the busy state, and with the number of access commands held by the holding unit being smaller than the third threshold value, the memory access state is the non-busy state. ### Claim 12 A method for controlling a memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, the method comprising: changing an output mode of the clock signal for data transfer based on a memory access state and outputting the clock signal for data transfer to the memory based on the output mode, wherein in a busy state as the memory access state, the changing sets a first output mode, and the outputting constantly outputs the clock signal for data transfer to the memory in the first output mode, and wherein in a non-busy state as the memory access state, the changing sets a second output mode, and the outputting outputs the clock signal for data transfer to the memory as needed in the second output mode. ### Claim 13 A non-transitory storage medium storing a program causing a memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, to execute a control method, the control method comprising: changing an output mode of the clock signal for data transfer based on a memory access state and outputting the clock signal for data transfer to the memory based on the output mode, wherein in a busy state as the memory access state, the changing sets a first output mode, and the outputting constantly outputs the clock signal for data transfer to the memory in the first output mode, and wherein in a non-busy state as the memory access state, the changing sets a second output mode, and the outputting outputs the clock signal for data transfer to the memory as needed in the second output mode.