# US 12,216,923 B2 · Computer system, memory expansion device and method for use in computer system

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- Number: US 12,216,923 B2
- Document ID: US12216923B2
- Status: Granted
- Kind: B2
- Application number: 18/064,500
- Filed: 2022-12-12
- Published: 2024-02-29
- Granted: 2025-02-04
- Earliest claimed: 2022-08-31
- Assignees: Alibaba (China) Co., Ltd.
- Applicants: Alibaba (China) Co., Ltd.
- Inventors: Yijin Guan; Tianchan Guan; Dimin Niu; Hongzhong Zheng
- Web page: https://patentgrep.com/patent/US12216923B2

## CPC

- G06F 3/0622: {in relation to access}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 1/1632: {External expansion units, e.g. docking stations}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0683: {Plurality of storage devices}
- G06F 15/17331: {Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present application provides a computer system, a memory expansion device and a method for use in the computer system. The computer system includes multiple hosts and multiple memory expansion devices; the memory expansion devices correspond to the hosts in a one-to-one manner. Each host includes a CPU and a memory; each memory expansion device includes a first interface and multiple second interfaces. The first interface is configured to allow each memory expansion device to communicate with the corresponding CPU via a first coherence interconnection protocol, and the second interface is configured to allow each memory expansion device to communicate with a portion of memory expansion devices via a second coherence interconnection protocol. Any two memory expansion devices communicate with each other via at least two different paths, and the number of memory expansion devices that at least one of the two paths passes through is not more than one.

## Claims

### Claim 1

A computer system, comprising:
a plurality of hosts, wherein each host comprises:
a CPU; and
a memory; and
a plurality of memory expansion devices, wherein the plurality of memory expansion devices correspond to the plurality of hosts in a one-to-one manner, wherein each memory expansion device comprises:
a first interface, configured to allow each memory expansion device to communicate with the corresponding CPU via a first coherence interconnection protocol; and
a plurality of second interfaces, configured to allow each memory expansion device to communicate with a portion of memory expansion devices of the plurality of memory expansion devices via a second coherence interconnection protocol;
wherein any two memory expansion devices of the plurality of memory expansion devices communicate with each other via at least two different paths, and the number of memory expansion devices that at least one of the two paths passes through is not more than one, and
wherein the CPU of a first host of the plurality of hosts is capable of accessing the memory of a second host of the plurality of hosts via the interconnected memory expansion devices that are operatively interconnected by the second coherence interconnection protocol.

### Claim 2 (depends on 1)

The computer system of claim 1, wherein each memory expansion device further comprises a memory interface controller, configured to covert a device memory access request from the first interface to a remote device memory access request, and convert a remote device memory access request from the second interface to a host memory access request.

### Claim 3 (depends on 2)

The computer system of claim 2, wherein the first coherence interconnection protocol is a CXL protocol, and the device memory access request conforms to CXL.mem sub-protocol of the CXL protocol.

### Claim 4 (depends on 2)

The computer system of claim 2, wherein the first coherence interconnection protocol is a CXL protocol, and the host memory access request conforms to CXL.cache sub-protocol of the CXL protocol.

### Claim 5 (depends on 2)

The computer system of claim 2, wherein the CPU of the first host of the plurality of hosts sends the device memory access request to a first memory expansion device corresponding to the first host, the memory interface controller of the first memory expansion device converts the device memory access request to the remote device memory access request, the first memory expansion device also sends the remote device memory access request to the second memory expansion device, the memory interface controller of the second memory expansion device converts the remote device memory access request to the host memory access request, the second memory expansion device also sends the host memory access request to the CPU of the second host of the plurality of hosts, so as to access the memory of the second host.

### Claim 6 (depends on 2)

The computer system of claim 2, wherein the CPU of the first host of the plurality of hosts sends the device memory access request to a first memory expansion device corresponding to the first host, the memory interface controller of the first memory expansion device converts the device memory access request to the remote device memory access request, the first memory expansion device also sends the remote device memory access request to the second memory expansion device, the second memory expansion device forwards the remote device memory access request to a third memory expansion device, the memory interface controller of the third memory expansion device converts the remote device memory access request to the host memory access request, the third memory expansion device also sends the host memory access request to the CPU of a third host of the plurality of hosts, so as to access the memory of the third host.

### Claim 7 (depends on 2)

The computer system of claim 2, wherein each memory expansion device further comprises a one-hop switch, coupled between the plurality of second interfaces and the memory interface controller, wherein when each memory expansion device receives the remote device memory access request from one of the plurality of second interfaces, the one-hop switch configured to selectively transfer the remote device memory access request to the memory interface controller, or sends out the remote device memory access request via another second interface of the plurality of second interfaces.

### Claim 8 (depends on 1)

The computer system of claim 1, wherein the plurality of hosts are mounted on a same rack.

### Claim 9 (depends on 1)

The computer system of claim 1, wherein the plurality of memory expansion devices are implemented using FPGA.

### Claim 10 (depends on 7)

The computer system of claim 7, wherein the plurality of memory expansion devices further comprise:
a packet engine, coupled between the one-hop switch and the memory interface controller.

### Claim 11 (depends on 1)

The computer system of claim 1, wherein the plurality of memory expansion devices further comprises near-memory processor.

### Claim 12 (depends on 1)

A memory expansion device, comprising:
the memory expansion device of the computer system of claim 1.

### Claim 13

A method for use in a computer system, wherein the computer system comprises a plurality of hosts and a plurality of memory expansion devices, wherein each host comprises a CPU and a memory, wherein the plurality of memory expansion devices correspond to the plurality of hosts in a one-to-one manner, and the method comprises the steps of:
allowing each memory expansion device to communicate with the corresponding CPU via first coherence interconnection protocol; and
allowing each memory expansion device to communicate with a portion of memory expansion devices of the plurality of memory expansion devices via a second coherence interconnection protocol, wherein any two memory expansion devices of the plurality of memory expansion devices communicate with each other via at least two different paths, and the number of memory expansion devices that at least one of the two paths passes through is not more than one,
wherein the CPU of a first host of the plurality of hosts is capable of accessing the memory of a second host of the plurality of hosts via the interconnected memory expansion devices.

### Claim 14 (depends on 13)

The method of claim 13, further comprising the step of:
allowing each memory expansion device to covert a device memory access request via the first coherence interconnection protocol to a remote device memory access request, and convert a remote device memory access request received via second coherence interconnection protocol to a host memory access request.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first coherence interconnection protocol is a CXL protocol, and the device memory access request conforms to CXL.mem sub-protocol of the CXL protocol.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first coherence interconnection protocol is a CXL protocol, and the host memory access request conforms to CXL.cache sub-protocol of the CXL protocol.

### Claim 17 (depends on 14)

The method of claim 14, further comprising the steps of:
allowing the CPU of the first host of the plurality of hosts to send the device memory access request to a first memory expansion device corresponding to the first host;
allowing the memory interface controller of the first memory expansion device to convert the device memory access request to the remote device memory access request;
allowing the first memory expansion device to send the remote device memory access request to the second memory expansion device;
allowing the memory interface controller of the second memory expansion device to convert the remote device memory access request to the host memory access request; and
allowing the second memory expansion device to send the host memory access request to the CPU of the second host of the plurality of hosts, so as to access the memory of the second host.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
allowing the CPU of the first host of the plurality of hosts to send the device memory access request to a first memory expansion device corresponding to the first host;
allowing the memory interface controller of the first memory expansion device to convert the device memory access request to the remote device memory access request;
allowing the first memory expansion device to send the remote device memory access request to the second memory expansion device;
allowing the second memory expansion device to forward the remote device memory access request to a third memory expansion device;
allowing the memory interface controller of the third memory expansion device to convert the remote device memory access request to the host memory access request; and
allowing the third memory expansion device to send the host memory access request to the CPU of a third host of the plurality of hosts, so as to access the memory of the third host.

### Claim 19 (depends on 14)

The method of claim 14, further comprising the step of:
when each memory expansion device receives the remote device memory access request, allowing each memory expansion device selectively to convert the remote device memory access request to the host memory access request, or send the remote device memory access request to another memory expansion device of the plurality of memory expansion devices via a second coherence interconnection protocol.