# US 12,216,916 B2 · Storage device and operating method thereof

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- Number: US 12,216,916 B2
- Document ID: US12216916B2
- Status: Granted
- Kind: B2
- Application number: 17/978,415
- Filed: 2022-11-01
- Published: 2023-05-11
- Granted: 2025-02-04
- Earliest claimed: 2021-11-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Youngsik Lee; Seunghyun Shin; Sunmi Yoo
- Web page: https://patentgrep.com/patent/US12216916B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/08: Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided are a storage device and an operating method thereof. The storage device includes a non-volatile memory including a plurality of memory regions and a storage controller configured to control the non-volatile memory through a performance path and at least one direct path, the storage controller including a buffer memory configured to store recovery data, wherein the storage controller writes the recovery data to the non-volatile memory through the at least one direct path in response to power being cut off and a fault being detected in the performance path, the performance path is a path for performing a write operation, a read operation, and an erase operation, and the at least one direct path is a path for performing only a write operation.

## Claims

### Claim 1

A storage device comprising: a non-volatile memory including a plurality of memory regions; and a storage controller including a plurality of cores and a buffer memory configured to store recovery data, the storage controller configured to communicate with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the storage controller configured to communicate with the non-volatile memory by, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation, detecting whether a fault is present in performance of the performance path, in response to a power being cut-off to the storage device, and in response to the fault being detected as present in the performance path while the power remains cut-off, moving the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory through the at least one direct path, wherein the performance path is for performing the write operation, the read operation, and the erase operation, and wherein the at least one direct path is for performing only the write operation.

### Claim 2 (depends on 1)

The storage device of claim 1, wherein the plurality of cores includes a first core configured to perform an operation related to an interface with a host, and a second core configured to perform an operation related to an interface with the non-volatile memory, the first core and the second core being included in the performance path, and in response to the fault being detected as present in the performance path while the power remains cut-off, the storage controller is configured to select one of the plurality of cores as a selected core and move the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory via a corresponding one of the plurality of direct paths.

### Claim 3 (depends on 2)

The storage device of claim 2, wherein
the at least one direct path includes a first direct path and a second direct path,
the first core is configured to write the recovery data to a first memory region, among the plurality of memory regions, through the first direct path, and
the second core is configured to write the recovery data to a second memory region, among the plurality of memory regions, through the second direct path.

### Claim 4 (depends on 1)

The storage device of claim 1, wherein the storage controller includes:
a plurality of first cores configured to perform an operation related to an interface with a host; and
a plurality of second cores configured to perform an operation related to an interface with the non-volatile memory,
the performance path includes the plurality of first cores and the plurality of second cores, and
in response to the power being cut off and the fault being detected in the performance path, each of the first cores is configured to write the recovery data to the non-volatile memory through the at least one direct path.

### Claim 5 (depends on 1)

The storage device of claim 1, wherein
the storage controller includes first to third cores sequentially included in the performance path, and
in response to the power being cut off and the fault being detected in the performance path, each of the first and second cores is configured to write the recovery data to the non-volatile memory through the at least one direct path.

### Claim 6 (depends on 5)

The storage device of claim 5, wherein the at least one direct path includes a first direct path, a second direct path and a third direct path,
the first core is configured to write the recovery data to a first memory region, among the plurality of memory regions, through the first direct path, and
the third core is configured to write the recovery data in a second memory region, among the plurality of memory regions, through the third direct path.

### Claim 7 (depends on 1)

The storage device of claim 1, wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data.

### Claim 8

An operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores and a buffer memory configured to store recovery data, the operating method comprising: communicating with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the communicating including, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation, detecting whether a fault is present in performance of the performance path, in response to a power being cut-off to the storage device, in response to the fault being detected as present in the performance path while the power remains cut-off, selecting one of the plurality of cores as a selected core and collecting recovery data written in the buffer memory, and moving the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory through the direct path corresponding to the selected core, wherein the performance path is for performing the write operation, the read operation, and the erase operation, and wherein the direct path is for performing only the write operation.

### Claim 9 (depends on 8)

The operating method of claim 8, further comprising:
writing the recovery data to the non-volatile memory through the performance path, in response to the power being cut off and the performance path being determined to be normal.

### Claim 10 (depends on 8)

The operating method of claim 8, wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data.

### Claim 11 (depends on 8)

The operating method of claim 8, further comprising:
determining the performance path to be normal, in response to each of write operations of writing first to n-th data of the recovery data to the non-volatile memory being completed within a first time.

### Claim 12 (depends on 8)

The operating method of claim 8, further comprising:
setting write information including position information indicating a position in the non-volatile memory to which the recovery data is to be written,
wherein the writing of the recovery data includes writing the recovery data to the non-volatile memory based on the write information.

### Claim 13 (depends on 12)

The operating method of claim 12, wherein
the non-volatile memory includes a plurality of memory regions, and
the writing of the recovery data includes writing the recovery data to a memory region among the plurality of memory regions corresponding to the selected core based on the write information.

### Claim 14 (depends on 8)

The operating method of claim 8, further comprising:
scanning a specified position in the non-volatile memory in response to the power being provided; and
opening the non-volatile memory in response to the recovery data being all written to the specified position.

### Claim 15 (depends on 8)

The operating method of claim 8, further comprising:
scanning a specified position in the non-volatile memory in response to the power being provided; and
in response to primary recovery data, among the recovery data, being written to the specified position, marking a data defect on user data corresponding to the primary recovery data.

### Claim 16 (depends on 15)

The operating method of claim 15, wherein the primary recovery data includes a user data digest, device metadata, and map data.

### Claim 17 (depends on 15)

The operating method of claim 15, further comprising:
in response to the primary recovery data, among the recovery data, being written to the specified position, transmitting, to a host, an error signal as a response signal according to the user data corresponding to the primary recovery data.

### Claim 18

An operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores and a buffer memory configured to store recovery data, the operating method comprising: setting write information for writing recovery data written in a buffer memory to the non-volatile memory; and communicating with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the communicating including, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation on the data, detecting whether a fault is present in performance of the performance path, in response to a power being cut-off to the storage device, and in response to the fault being detected as present in the performance path while the power remains cut-off, selecting, based on the write information, one of the plurality of cores as a selected core and collecting the recovery data, and moving the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory through the direct path corresponding to the selected core, wherein the performance path includes the plurality of cores, and the direct path includes one of the plurality of cores.

### Claim 19 (depends on 18)

The operating method of claim 18, further comprising:
scanning a specified position in the non-volatile memory in response to the power being provided; and
opening the non-volatile memory in response to the recovery data being all written to the specified position.

### Claim 20 (depends on 19)

The operating method of claim 19, further comprising:
marking a data defect on user data corresponding to primary recovery data among the recovery data, in response to the primary recovery data being written to a specified position, and
wherein the primary recovery data includes a user data digest, device metadata, and map data.