# US 12,216,914 B2 · Apparatus and method for power-loss data protection in a system

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- Number: US 12,216,914 B2
- Document ID: US12216914B2
- Status: Granted
- Kind: B2
- Application number: 17/958,498
- Filed: 2022-10-03
- Published: 2023-10-19
- Granted: 2025-02-04
- Earliest claimed: 2022-04-15
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jin Pyo Kim; Ju Hyun Kim; Jong Soon Park; Woong Sik Shin; Woo Young Yang
- Web page: https://patentgrep.com/patent/US12216914B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory system includes a memory device including a first memory block used for power-loss data protection and a controller coupled to the memory device. The controller includes a hardware layer and a firmware layer. The hardware layer checks whether at least one write data entry belongs to a programmable range in the memory device after power loss occurs, determines whether a logical address associated with the at least one write data entry is repeated, and programs the at least one write data entry in the first memory block.

## Claims

### Claim 1

A memory system comprising:
a memory device including a first memory block used for power-loss data protection; and
a controller coupled to the memory device, the controller including a hardware layer and a firmware layer, the hardware layer configured to:
check whether at least one write data entry input from an external device to be programmed in the memory device belongs to a programmable range in the memory device after power loss occurs,
determine whether a logical address associated with the at least one write data entry is repeated, and
program the at least one write data entry in the first memory block after the checking and the determining, wherein:
the firmware layer is configured to process a write data entry for a program operation, and
the controller is configured to set an identifier to the write data entry completely processed by the firmware layer.

### Claim 2 (depends on 1)

The memory system according to claim 1, wherein the hardware layer comprises:
a first processor configured to determine whether the at least one write data entry belong to the programmable range;
a second processor configured to determine whether the logical address associated with the at least one write data entry is repeated, set a tag to a write data entry associated with an old logical address of repeated logical addresses, divide or combine the at least one data entry to correspond to a program operation unit;
a third processor configured to exclude the write data entry with the tag from a program data group and output the program data group of which size or amount is equal to or less than a threshold established for the memory device to perform a program operation for the power-loss data protection; and
a fourth processor configured to transfer the program data group output from the third processor to a physical layer for transmission to the memory device.

### Claim 3 (depends on 2)

The memory system according to claim 2,
wherein the hardware layer is further configured to receive a barrier message informing that all write data entries associated with the power-loss data protection have been transmitted, and transmit the barrier message to the firmware layer, and
wherein the firmware layer is configured to determine whether a pending data entry is associated with the power-loss data protection in response to the barrier message and transfer the pending data entry to the hardware layer when the pending data entry is associated with the power-loss data protection.

### Claim 4 (depends on 1)

The memory system according to claim 1, wherein the first memory block comprises plural pages, each page including a data region storing the write data entry and a spare region storing the identifier corresponding to the write data entry, the data region including plural memory cells, each memory cell storing 1-bit data.

### Claim 5 (depends on 1)

The memory system according to claim 1,
wherein the hardware layer is further configured to determine whether data coherency regarding a data entry is checked during a data input/output operation when no power loss occurs,
wherein the firmware layer is configured to process the data entry for a read operation or a program operation when the data coherency regarding the write data entry is checked, and
wherein the hardware layer is further configured to process the data entry for the read operation or the program operation when the data coherency regarding the data entry is not checked.

### Claim 6 (depends on 5)

The memory system according to claim 5, wherein the data entry regarding the data coherency which is to be checked is associated with at least one of:
a program operation following garbage collection;
an unaligned program operation involving a Read/Modify/Write (RMW) operation; and
a map data operation for updating, with a delay or conditionally, metadata which is stored in the memory device.

### Claim 7 (depends on 5)

The memory system according to claim 5, wherein the hardware layer is further configured to complete, when no power loss occurs, the data input/output operation regarding the data entry after the firmware layer processes the data coherency regarding the data entry.

### Claim 8 (depends on 1)

The memory system according to claim 1, wherein a program operation regarding the at least one write data entry involves at least one of a map update or journaling, and the hardware layer or the firmware layer is further configured to perform the map update or the journaling.

### Claim 9 (depends on 1)

The memory system according to claim 1, wherein the hardware layer and the firmware layer are further configured to check a descriptor used for sharing information regarding the at least one write data entry to recognize handling, transfer, allocation, or release of the at least one write data entry.

### Claim 10 (depends on 1)

The memory system according to claim 1, further comprising an auxiliary power supply unit configured to supply auxiliary power to the controller and the memory device when the power loss occurs.

### Claim 11 (depends on 1)

The memory system according to claim 1, wherein the hardware layer is further configured to store the at least one write data entry in the memory device, when the at least one write data entry is input from an external device and an early completion regarding the at least one write data entry is transmitted to the external device before the power loss occurs.

### Claim 12 (depends on 11)

The memory system according to claim 11, wherein the controller transmits the early completion to the external device for the at least one write data entry which belongs to the programmable range which is preset for securely programming a size or an amount of write data in the memory device even though the power loss occurs.

### Claim 13 (depends on 1)

The memory system according to claim 1,
wherein the controller is configured to read, when power is resumed after the power loss, the at least one write data entry and the identifier associated with the at least one write data entry from the first memory block, and
wherein the controller is further configured to use at least one of the hardware layer or the firmware layer to perform a recovery operation regarding the at least one write data entry based on the identifier.

### Claim 14 (depends on 13)

The memory system according to claim 13,
wherein the memory device further comprises a second memory block including plural memory cells, each memory cell storing multi-bit data, and
wherein the controller is further configured to program, in the second memory block, a write data entry generated through the recovery operation.

### Claim 15

A method for operating a memory system, the method comprising:
performing a data input/output operation through a hardware layer and a firmware layer; and
programming, through the hardware layer, at least one write data entry in a designated memory block, after checking whether the at least one write data entry input from an external device to be programmed in the memory device belongs to a programmable range in the memory device after power loss occurs and determining whether a logical address associated with the at least one write data entry is repeated,
wherein the programming comprises:
generating an event for power-loss data protection after power loss occurs;
transferring information regarding a data input/output operation associated with a write data entry processed from the firmware layer to the hardware layer in response to the event;
setting an identifier to the write data entry when the write data entry is completely processed for a program operation through the firmware layer; and
programming the at least one write data entry, including the write data entry, collected by the hardware layer in the designated memory block.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the programming comprises:
determining whether the at least one write data entry belongs to the programmable range;
determining whether the logical address associated with the at least one write data entry is repeated;
setting a tag to a write data entry associated with an old logical address of repeated logical addresses;
dividing or combining the at least one data entry to correspond to a program operation unit;
excluding the write data entry with the tag from a program data group;
outputting the program data group of which size or amount is equal to or less than a threshold established for the memory device to perform a program operation for the power-loss data protection; and
transferring the program data group to a physical layer for transmission to the memory device.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
receiving, through the hardware layer, a barrier message informing that all write data entries associated with the power-loss data protection have been transmitted to transmit the barrier message to the firmware layer; and
determining, the firmware layer, whether a pending data entry is associated with the power-loss data protection in response to the barrier message to transfer the pending data entry to the hardware layer when the pending data entry is associated with the power-loss data protection.

### Claim 18 (depends on 15)

The method according to claim 15, further comprising recovering the at least one write data entry stored in the designated memory block when power is resumed after the power loss,
wherein the recovering comprises:
reading, when power is resumed after the power loss, the at least one write data entry and the identifier associated with the at least one write data entry from the designated memory block; and
performing a recovery operation regarding the at least one write data entry through the hardware layer or the firmware layer based on the identifier.