# US 12,216,907 B2 · Method of improving programming operations in 3D NAND systems

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- Number: US 12,216,907 B2
- Document ID: US12216907B2
- Status: Granted
- Kind: B2
- Application number: 18/082,265
- Filed: 2022-12-15
- Published: 2024-05-23
- Granted: 2025-02-04
- Earliest claimed: 2022-11-23
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Zhe Luo; Da Li; Feng Xu; Yaoyao Tian; Jianquan Jia; XiangNan Zhao
- Web page: https://patentgrep.com/patent/US12216907B2

## CPC

- G06F 3/0613: {in relation to throughput}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.

## Claims

### Claim 1

A method for programming a memory device, the method comprising:
performing a programming operation on a memory cell, wherein the memory cell is connected to a bit line and is controlled by a word line, wherein performing the programming operation comprises:
applying a first programming voltage signal to the word line to program the memory cell into a first programmed state;
applying a first voltage to the bit line;
subsequent to the applying the first voltage, performing a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
determining a classification of the memory cell based on the verify operation;
applying a second voltage to the bit line based on the determined classification;
applying a second programming voltage signal to the word line to program the memory cell into the first programmed state;
applying a third voltage to the bit line;
applying a third programming voltage signal to the word line to program the memory cell into the first programmed state; and
applying a fourth voltage to the bit line.

### Claim 2 (depends on 1)

The method of claim 1, wherein the applying the first voltage comprises applying a voltage larger than zero.

### Claim 3 (depends on 1)

The method of claim 1, wherein a target voltage of the second programmed state is lower than a target voltage of the first programmed state.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing the verify operation comprises comparing a threshold voltage of the memory cell with a read reference voltage, wherein the read reference voltage is the second verify voltage of the second programmed state.

### Claim 5 (depends on 4)

The method of claim 4, wherein the determining the classification of the memory cell based on the verify operation comprises:
determining a classification of the memory cell as a first classification when the threshold voltage is larger than the read reference voltage, or
determining a classification of the memory cell as a second classification when the threshold voltage is smaller than the read reference voltage.

### Claim 6 (depends on 5)

The method of claim 5, wherein the applying the second voltage is applied so as to be equal to the first voltage based on the determined first classification of the memory cell, or as a zero voltage based on the determined second classification of the memory cell.

### Claim 7 (depends on 1)

The method of claim 1, wherein the third voltage is larger than the second voltage.

### Claim 8

A three-dimensional (3D) NAND memory device, comprising:
a NAND string including a cell to be inhibited to program;
a word line driver;
a bit line driver; and
a controller configured to control the word line driver and the bit line driver to:
apply a first programming voltage signal to a word line to program a memory cell into a first programmed state;
apply a first voltage to a bit line;
subsequent to the applying the first voltage, perform a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
determine a classification of the memory cell based on the verify operation;
apply a second voltage to the bit line based on the determined classification;
apply a second programming voltage signal to the word line to program the memory cell into the first programmed state;
apply a third voltage to the bit line;
apply a third programming voltage signal to the word line to program the memory cell into the first programmed state; and
apply a fourth voltage to the bit line.

### Claim 9 (depends on 8)

The 3D NAND memory device of claim 8, wherein the applying the first voltage comprises applying a voltage larger than zero.

### Claim 10 (depends on 8)

The 3D NAND memory device of claim 8, wherein a target voltage of the second programmed state is lower than a target voltage of the first programmed state.

### Claim 11 (depends on 8)

The 3D NAND memory device of claim 8, wherein performing the verify operation comprises comparing a threshold voltage of the memory cell with a read reference voltage, wherein the read reference voltage is the second verify voltage of the second programmed state.

### Claim 12 (depends on 11)

The 3D NAND memory device of claim 11, wherein the determining the classification of the memory cell based on the verify operation comprises:
determining a classification of the memory cell as a first classification when the threshold voltage is larger than the read reference voltage, or
determining a classification of the memory cell as a second classification when the threshold voltage is smaller than the read reference voltage.

### Claim 13 (depends on 12)

The 3D NAND memory device of claim 12, wherein the applying the second voltage is applied so as to be equal to the first voltage based on the determined first classification of the memory cell, or as a zero voltage based on the determined second classification of the memory cell.

### Claim 14 (depends on 8)

The 3D NAND memory device of claim 8, wherein the third voltage is larger than the second voltage.

### Claim 15

A non-transitory medium having instructions stored thereon that, upon execution by at least one controller, cause the at least one controller to perform a method of performing a programming operation of a memory device, the method comprising:
applying a first programming voltage signal to a word line to program a memory cell into a first programmed state;
applying a first voltage to a bit line;
subsequent to the applying the first voltage, performing a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
determining a classification of the memory cell based on the verify operation;
applying a second voltage to the bit line based on the determined classification;
applying a second programming voltage signal to the word line to program the memory cell into the first programmed state;
applying a third voltage to the bit line;
applying a third programming voltage signal to the word line to program the memory cell into the first programmed state; and
applying a fourth voltage to the bit line.

### Claim 16 (depends on 15)

The non-transitory medium of claim 15, wherein the applying the first voltage comprises applying a voltage larger than zero.

### Claim 17 (depends on 15)

The non-transitory medium of claim 15, wherein a target voltage of the second programmed state is lower than a target voltage of the first programmed state.

### Claim 18 (depends on 15)

The non-transitory medium of claim 15, wherein performing the verify operation comprises comparing a threshold voltage of the memory cell with a read reference voltage, wherein the read reference voltage is the second verify voltage of the second programmed state.

### Claim 19 (depends on 18)

The non-transitory medium of claim 18, wherein the determining the classification of the memory cell based on the verify operation comprises:
determining a classification of the memory cell as a first classification when the threshold voltage is larger than the read reference voltage, or
determining a classification of the memory cell as a second classification when the threshold voltage is smaller than the read reference voltage.

### Claim 20 (depends on 19)

The non-transitory medium of claim 19, wherein the applying the second voltage is applied so as to be equal to the first voltage based on the determined first classification of the memory cell, or as a zero voltage based on the determined second classification of the memory cell.