# US 12,216,906 B2 · Host techniques for stacked memory systems

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- Number: US 12,216,906 B2
- Document ID: US12216906B2
- Status: Granted
- Kind: B2
- Application number: 17/942,163
- Filed: 2022-09-11
- Published: 2023-01-05
- Granted: 2025-02-04
- Earliest claimed: 2019-12-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Joseph T. Pawlowski
- Web page: https://patentgrep.com/patent/US12216906B2

## CPC

- G06F 3/0613: {in relation to throughput}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 12/0862: with prefetch
- G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache
- G11C 2207/2245: Memory devices with an internal cache buffer
- G11C 2207/2272: Latency related aspects
- G11C 2211/4066: Pseudo-SRAMs
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.

## Claims

### Claim 1

A system comprising:
a storage device including a first memory device of a first type of volatile memory and a second memory device of a second type of volatile memory;
a host device coupled to the storage device, the host device configured to issue commands to the storage device to store and retrieve information of the system; and
a logic die comprising:
an interface circuit configured to receive the commands from the host device using an external bus; and
a controller configured to control data communication between the interface circuit and the first memory device, wherein the second memory device is configured as an exclusive data target for exchanging data between the storage device and the host device, and wherein each respective data exchange, using the external bus between the storage device and the host device, includes data passed via the second memory device.

### Claim 2 (depends on 1)

The system of claim 1, wherein the interface circuit is configured to directly access the second memory device in response to a first command of the commands from the host device.

### Claim 3 (depends on 1)

The system of claim 1, wherein the first memory device comprises a dynamic random access memory (DRAM) device, and wherein the second memory device comprises a static random access memory (SRAM) device, and wherein the first and second memory devices have different latency characteristics.

### Claim 4 (depends on 1)

The system of claim 1, wherein the external bus comprises a data bus, a row command bus, and a column command bus.

### Claim 5 (depends on 4)

The system of claim 4, wherein a first three bits of the row command bus are configured to provide a command identifier upon a first transition of a clock signal of the row command bus, and wherein the controller is configured to directly access the second memory device when the first three bits of the row command bus are HIGH, LOW, HIGH, respectively, upon the first transition of the clock signal of the row command bus.

### Claim 6 (depends on 1)

The system of claim 1, wherein the host device includes a memory map of the storage device and latency information associated with each command of the commands.

### Claim 7 (depends on 6)

The system of claim 6, wherein the host device is configured to sort pending commands according to the latency information and to use commands for the first type of volatile memory and commands for the second type of volatile memory to provide a high-efficiency command schedule.

### Claim 8 (depends on 6)

The system of claim 6, wherein the host device is configured to sort pending commands according to the latency information to provide a command schedule, and wherein the commands include read and write commands for each of the first and second memory devices.

### Claim 9

A method comprising:
mapping volatile memory of a memory package at a host device;
maintaining command latency information of multiple volatile memory types of the memory package;
sorting pending commands according to a command latency associated with each of the volatile memory types of the multiple volatile memory types; and
determining a command schedule for a data interface between the host device and the memory package using commands for a first type of volatile memory and commands for a second type of volatile memory;
wherein a latency of a command for the first type of volatile memory is greater than a combined latency of multiple, serially-issued commands for the second type of volatile memory.

### Claim 10 (depends on 9)

The method of claim 9, comprising:
transmitting, from the host device to the memory package, a first command of the command schedule to access the first type of volatile memory, and executing the first command at the memory;
transmitting, from the host device to the memory package, multiple second commands of the command schedule to access the second type of volatile memory; and
executing the multiple second commands at the memory package during the latency of the first command.

### Claim 11 (depends on 10)

The method of claim 10, wherein executing the first command and executing the multiple second commands includes routing data associated with each of the commands through the second type of volatile memory.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first type of volatile memory is dynamic random-access memory (DRAM), and wherein the second type of volatile memory is static random-access memory (SRAM).

### Claim 13 (depends on 9)

The method of claim 9, wherein determining the command schedule for the data interface includes intermixing read and/or write commands for each of the first and second types of volatile memory.

### Claim 14

A stacked memory device comprising:
a first memory device of a first type of volatile memory;
a second memory device of a second type of volatile memory; and
a logic die comprising:
an interface circuit configured to receive a commands from a host device using an external bus, wherein the interface circuit is configured to directly access the second memory device; and
a controller configured to control data communication between the interface circuit and the first memory device, wherein each respective data exchange between the host device and the stacked memory device passes data via the second memory device.

### Claim 15 (depends on 14)

The stacked memory device of claim 14, wherein the first memory device comprises a dynamic random access memory (DRAM) device, and wherein the second memory device comprises a static random access memory (SRAM) device, and wherein the first and second memory devices have different latency characteristics.

### Claim 16 (depends on 15)

The stacked memory device of claim 15, wherein the second memory device comprises a prefetch buffer configured to store information from the first memory device.

### Claim 17 (depends on 16)

The stacked memory device of claim 16, wherein the controller comprises a command decoder configured to route commands from the external bus to at least one of the prefetch buffer, the first memory device, and the second memory device.

### Claim 18 (depends on 14)

The stacked memory device of claim 14, wherein the external bus comprises a data bus, a row command bus, and a column command bus.