# US 12,216,610 B2 · Computational array microprocessor system using non-consecutive data formatting

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,216,610 B2
- Document ID: US12216610B2
- Status: Granted
- Kind: B2
- Application number: 18/335,944
- Filed: 2023-06-15
- Published: 2023-12-21
- Granted: 2025-02-04
- Earliest claimed: 2017-07-24
- Assignees: Tesla, Inc.
- Applicants: Tesla, Inc.
- Inventors: Emil Talpes; William McGee; Peter Joseph Bannon
- Web page: https://patentgrep.com/patent/US12216610B2

## CPC

- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 15/8023: {Two dimensional arrays, e.g. mesh, torus}
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/048: Activation functions
- G06N 3/063: using electronic means
- G06N 3/08: Learning methods
- G06F 2207/4824: Neural networks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values.

## Claims

### Claim 1

A microprocessor system, comprising:
a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value of a group of values addressed from memory and a first portion of the group of values operated by the plurality of computation units are synchronously provided together to the computational array to be processed in parallel in a first computation processing; and
a hardware data formatter configured to, based on a stride, provide the first portion of the group of values to the computational array for the first computation processing and identify a second portion of the group of values not provided for the first computation processing, wherein the hardware data formatter is configured to perform a cache check to obtain the first portion of the group of values,
and wherein the second portion of the group of values are stored and provided, by the hardware data formatter, to the computational array for a second computation processing subsequent to the first computation processing.

### Claim 2 (depends on 1)

The system of claim 1, wherein the first portion of the group of values located consecutively in the memory and the second portion of the group of values located consecutively in the memory, and the first portion is not located consecutively in the memory from the second portion.

### Claim 3 (depends on 2)

The system of claim 2, wherein the first portion is retrieved from a cache using a single cache read.

### Claim 4 (depends on 2)

The system of claim 2, wherein the first portion of the group of values and the second portion of the group of values are retrieved from a single cache line.

### Claim 5 (depends on 2)

The system of claim 2, wherein the cache check is performed for the first portion of the group of values based on determining whether a first value and a last value for the first portion of the group of values are stored in a cache.

### Claim 6 (depends on 2)

The system of claim 2, wherein the hardware data formatter is configured to determine a corresponding start memory address for each of the first portion of the group of values and the second portion of the group of values.

### Claim 7 (depends on 6)

The system of claim 6, wherein the hardware data formatter is configured to determine a corresponding end memory address for each of the first portion of the group of values and the second portion of the group of values.

### Claim 8 (depends on 6)

The system of claim 6, wherein the cache check is performed for each of the first portion of the group of values and the second portion of the group of values based on determining whether a value stored at the determined starting memory addresses for the first portion of the group of values and the second portion of the group of values has been cached.

### Claim 9 (depends on 1)

The system of claim 1, wherein the computational array is configured to receive at least two vector input operands.

### Claim 10 (depends on 1)

The system of claim 1, wherein each computation unit of the plurality of computation units is configured to perform a dot-product component operation using the group of values in parallel.

### Claim 11 (depends on 1)

The system of claim 1, wherein each computation unit of the plurality of computation units includes an arithmetic logic unit, an accumulator, and a shadow register.

### Claim 12 (depends on 1)

The system of claim 1, wherein the group of values corresponds to an input channel of vision data.

### Claim 13 (depends on 1)

The system of claim 1, wherein the group of values corresponds to sensor data.

### Claim 14 (depends on 13)

The system of claim 13, wherein the sensor data is non-image sensor data.

### Claim 15 (depends on 14)

The system of claim 14, wherein the non-image sensor data includes ultrasonic, radar, or LiDAR data.

### Claim 16 (depends on 1)

The system of claim 1, wherein the group of values corresponds to a convolution filter.

### Claim 17 (depends on 16)

The system of claim 16, wherein the convolution filter is constructed to identify features of an input data.

### Claim 18 (depends on 1)

The system of claim 1, wherein the memory is configured to dynamically adjust an allocation between a first portion of the memory for a data input and a second portion of the memory for a weight input.

### Claim 19 (depends on 1)

The system of claim 1, wherein subsets of values included in the group of values are selected based at least in part on a padding parameter or a stride parameter.

### Claim 20

A method comprising:
receiving a computational operation;
receiving a data formatting operation at a hardware data formatter;
retrieving, based on a stride and via the hardware data formatter, a first group of values associated with an input data, wherein the hardware data formatter performs a cache check to retrieve the first group of values, wherein the first group of values includes a first subset of values, and wherein a second subset of values is identified via the hardware data formatter;
retrieving a second group of values associated with a weight data;
providing in parallel the first subset of values and the second group of values to a computational array microprocessor, wherein the second subset is not provided; and
processing the first group of values and the second group of values as operands in parallel using the computational array microprocessor and the computational operation, wherein the second subset is subsequently processed by the computational array microprocessor using a second computational operation.