# US 12,216,599 B2 · Peripheral component interconnect express (PCIe) device method for delaying command operations based on generated throughput analysis information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,599 B2 - Document ID: US12216599B2 - Status: Granted - Kind: B2 - Application number: 17/567,609 - Filed: 2022-01-03 - Published: 2022-09-22 - Granted: 2025-02-04 - Earliest claimed: 2021-03-18 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Yong Tae Jeon; Ji Woon Yang; Sang Hyun Yoon; Se Hyeon Han - Web page: https://patentgrep.com/patent/US12216599B2 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 13/4295: {using an embedded synchronisation} - G06F 2213/0024: Peripheral component interconnect [PCI] - G06F 2213/0026: PCI express - G06F 2213/2806: Space or buffer allocation for DMA transfers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generato and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command. ## Claims ### Claim 1 A Peripheral Component Interconnect Express (PCIe) device, comprising: a performance analyzer configured to measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions; a delay time information generator configured to generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information; and a command fetcher configured to fetch a target command from a host based on a delay time of a function corresponding to the target command. ### Claim 2 (depends on 1) The PCIe device according to claim 1, the performance analyzer comprises: a throughput calculator calculates a throughput of each of the plurality of functions based on occupation rates of the plurality of functions for a data path shared between the plurality of functions; and a throughput analysis information generator configured to generate the throughput analysis information for each of the plurality of functions. ### Claim 3 (depends on 2) The PCIe device according to claim 2, wherein the throughput calculator calculates the occupation rates of the plurality of functions based on a number of transaction layer packets of each function processed through the data path per unit time. ### Claim 4 (depends on 1) The PCIe device according to claim 1, wherein the PCIe device further comprises a command lookup table storage configured to store command-related information on the target command to be fetched from the host and the delay time of the function corresponding to the target command. ### Claim 5 (depends on 4) The PCIe device according to claim 4, wherein the command fetcher delays the command fetch operation for the target command when the delay time of the function has not elapsed from a time point at which the command-related information is stored. ### Claim 6 (depends on 1) The PCIe device according to claim 1, wherein, for each of the plurality of functions, the throughput analysis information includes at least one of information indicating whether a throughput exceeds a throughput limit, an excess ratio of the throughput to the throughput limit, a residual ratio of the throughput to the throughput limit, information about whether each of the plurality of functions is in an idle state, and information about whether the throughput is lower than a minimum performance threshold value set for each of the plurality of functions. ### Claim 7 (depends on 6) The PCIe device according to claim 6, wherein the delay time information generator is configured to increase the delay time of the function based on the excess ratio when the throughput exceeds the throughput limit. ### Claim 8 (depends on 6) The PCIe device according to claim 6, wherein the delay time information generator is configured to decrease the delay time of the function based on the residual ratio when the throughput is within the throughput limit, and wherein the function has delay times higher than an initial value, among the plurality of functions. ### Claim 9 (depends on 6) The PCIe device according to claim 6, wherein the delay time information generator sets a delay time of a function that is in an idle state and a delay time of a function, for which the throughput is lower than the minimum performance threshold value, among the plurality of functions, to an initial value. ### Claim 10 (depends on 1) The PCIe device according to claim 1, wherein the throughput includes a read throughput corresponding to a read operation and a write throughput corresponding to a write operation of each of the plurality of functions, wherein the throughput analysis information includes read throughput analysis information corresponding to the read operation and write throughput analysis information corresponding to the write operation, and wherein the delay time includes a read delay time corresponding to the read operation and a write delay time corresponding to the write operation. ### Claim 11 (depends on 1) The PCIe device according to claim 1, the PCIe device further comprises a traffic class controller configured to allocate traffic class values to transaction layer packets received from the plurality of functions based on the throughputs of the plurality of functions. ### Claim 12 (depends on 11) The PCIe device according to claim 11, wherein the traffic class controller is configured to, whenever a ranking of the throughputs of the plurality of functions varies, reallocate the traffic class values of the transaction layer packets based on the varied ranking. ### Claim 13 (depends on 11) The PCIe device according to claim 11, wherein the traffic class controller is configured to allocate a default value as initial values for traffic classes of the transaction layer packets received from the plurality of functions. ### Claim 14 (depends on 11) The PCIe device according to claim 11, wherein the traffic class controller is configured to allocate a default value as a traffic class value of a transaction layer packet received from a function for which a throughput is greater than a threshold value, among the plurality of functions. ### Claim 15 (depends on 11) The PCIe device according to claim 11, wherein the traffic class controller is configured to allocate a default value as a traffic class value of a transaction layer packet received from an interrupted function, among the plurality of functions.