# US 12,216,598 B2 · Field programmable gate array (FPGA) for implementing data transmission by using built-in edge module

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- Number: US 12,216,598 B2
- Document ID: US12216598B2
- Status: Granted
- Kind: B2
- Application number: 18/347,642
- Filed: 2023-07-06
- Published: 2023-11-09
- Granted: 2025-02-04
- Earliest claimed: 2023-03-22
- Assignees: Wuxi Esiontech Co., Ltd.
- Applicants: Wuxi Esiontech Co., Ltd.
- Inventors: Yueer Shan; Yanfeng Xu; Jicong Fan; Tong Liu; Hua Yan
- Web page: https://patentgrep.com/patent/US12216598B2

## CPC

- G06F 13/20: for access to input/output bus
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0813: with a network or matrix configuration
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0857: {by multiple requestors}
- G06F 15/17: using an input/output type connection, e.g. channel, I/O port
- G06F 15/78: comprising a single central processing unit
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 2212/1016: Performance improvement
- G06F 2212/254: Distributed memory
- G06F 2212/261: Storage comprising a plurality of storage devices
- G06F 2212/284: being distributed
- G06F 2212/60: Details of cache memory
- G06F 2213/40: Bus coupling
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An FPGA for implementing data transmission by using a built-in edge module is provided. The FPGA is provided with a built-in edge module. A read port of each resource module connected to the edge module in the FPGA is separately connected to a winding architecture and the edge module, and/or a write port of each resource module connected to the edge module in the FPGA is separately connected to the winding architecture and the edge module. The edge module includes a read/write controller and a cache unit. The read/write controller simultaneously reads data from read ports of a plurality of resource modules and temporarily stores the read data in the cache unit. Alternatively, the read/write controller simultaneously writes temporarily stored data in the cache unit into write ports of the plurality of resource modules.

## Claims

### Claim 1

A field programmable gate array (FPGA) for implementing a data transmission by using a built-in edge module, wherein the FPGA is provided with the built-in edge module, wherein the built-in edge module is connected to a plurality of resource modules within the FPGA, wherein a read port of each of the plurality of resource modules is separately connected to a winding architecture and the edge module, and/or a write port of each of the plurality of resource modules is separately connected to the winding architecture and the edge module; and
the edge module comprises a read/write controller and a built-in cache unit, wherein the read/write controller simultaneously reads data from read ports of the plurality of resource modules and temporarily stores the data in the cache unit, or the read/write controller simultaneously writes the data temporarily stored in the cache unit into write ports of the plurality of resource modules.

### Claim 2 (depends on 1)

The FPGA according to claim 1, wherein the built-in cache unit of the edge module comprises a plurality of read cache units and at least one write cache unit, wherein the data simultaneously read by the read/write controller from the read ports of the plurality of resource modules is temporarily stored in the plurality of read cache units respectively, and each of the plurality of read cache units is configured to temporarily store data read from a read port of one resource module; and
the data simultaneously written by the read/write controller into the write ports of the plurality of resource modules comes from the at least one write cache unit, and data in each of the at least one write cache unit is simultaneously written into a write port of at least one resource module.

### Claim 3 (depends on 2)

The FPGA according to claim 2, wherein each of the plurality of resource modules is connected to the edge module and has a read port and a write port, and the read/write controller simultaneously reads the data from the read port of the one resource module and writes the data into a write port of the one resource module.

### Claim 4 (depends on 2)

The FPGA according to claim 2, wherein each of the plurality of built-in read cache units of the edge module is separately connected to read ports of a plurality of resource modules, a read port of each of the plurality of resource modules is connected to the corresponding read cache unit by using a three-state selector, and the read/write controller controls on/off of each three-state selector and reads data from a read port of one of the plurality of resource modules connected to the read cache unit each time; and
each of the at least one built-in write cache unit of the edge module is separately connected to write ports of a plurality of resource modules, and the read/write controller writes data in one write cache unit into write ports of all connected resource modules or into write ports of some connected resource modules each time.

### Claim 5 (depends on 2)

The FPGA according to claim 2, wherein each of the plurality of built-in read cache units of the edge module is separately connected to the at least one write cache unit,
data written by the read/write controller into a write port of a first resource module is data read by the read/write controller from a read port of a second resource module,
the read/write controller reads the data from the read port of the second resource module and temporarily stores the read data in a read cache unit connected to the read port of the second resource module, and
the read/write controller writes data in the read cache unit connected to the read port of the second resource module into a write cache unit connected to the write port of the first resource module, and writes data in the write cache unit connected to the first resource module into the write port of the first resource module.

### Claim 6 (depends on 5)

The FPGA according to claim 5, wherein data simultaneously written by the read/write controller into write ports of a plurality of first resource modules is data read by the read/write controller from a read port of at least one second resource module; and data read from a read port of each second resource module is written into a write port of at least one first resource module.

### Claim 7 (depends on 6)

The FPGA according to claim 6, wherein each of the plurality of resource modules is connected to the edge module and is arranged based on an array structure, a same read cache unit is connected to read ports of a plurality of resource modules located in a same column, and a same write cache unit is connected to write ports of a plurality of resource modules located in a same column; and
the read/write controller simultaneously reads data from read ports of a plurality of second resource modules located in a same row, or the read/write controller simultaneously writes data into write ports of a plurality of first resource modules located in a same row.

### Claim 8 (depends on 2)

The FPGA according to claim 2, wherein the cache unit of the edge module is further connected to an off-chip read/write port of the FPGA, and the data read by the read/write controller from the read port of the resource module and temporarily stored in the read cache unit is transmitted to an outside of the FPGA through the off-chip read/write port, or the data written by the read/write controller into the write port of the resource module is transferred from the outside of the FPGA through the off-chip read/write port and temporarily stored in the at least one write cache unit; and
the off-chip read/write port of the FPGA is a high-speed serial port and/or a double data rate (DDR) input/output (I/O) port.

### Claim 9 (depends on 7)

The FPGA according to claim 7, wherein the edge module is simultaneously connected to a plurality of off-chip read/write ports, and the read/write controller simultaneously transmits the data temporarily stored in the plurality of read cache units to an outside of the FPGA through the plurality of off-chip read/write ports respectively, or the read/write controller simultaneously writes data input from the outside of the FPGA into a plurality of write cache units through the plurality of off-chip read/write ports.

### Claim 10 (depends on 7)

The FPGA according to claim 7, wherein the built-in cache unit of the edge module is configured in a first in first out (FIFO) memory, and a read/write speed of an off-chip read/write port for the cache unit matches a read/write speed of the read/write controller for the resource module.

### Claim 11 (depends on 2)

The FPGA according to claim 2, wherein the edge module further comprises a read/write signal generation circuit connected to a read/write control port of the resource module, and the read/write controller generates a read/write control signal by using the read/write signal generation circuit and sends the read/write control signal to the read/write control port of the resource module, and reads the data from the read ports of the plurality of resource modules or writes the data into the write ports of the plurality of resource modules simultaneously based on the read/write control signal.

### Claim 12 (depends on 11)

The FPGA according to claim 11, wherein the edge module comprises one read/write signal generation circuit connected to read/write control ports of all the resource modules; or the edge module comprises a plurality of read/write signal generation circuits, wherein each of the plurality of read/write signal generation circuits is connected to a read/write control port of at least one resource module, and each of the plurality of read/write signal generation circuits sends the read/write control signal to the read/write control port of the connected resource module.

### Claim 13 (depends on 11)

The FPGA according to claim 11, wherein each of the plurality of resource modules is connected to the edge module and is a block random access memory (BRAM), and a read/write control port of each BRAM comprises a read address port, a read enabling port, a write address port, and a write enabling port;
the built-in read/write signal generation circuit of the edge module comprises a read address generator, a read enabling generator, a write address generator, and a write enabling generator, the read address generator is connected to the read address port of the BRAM, the read enabling generator is connected to the read enabling port of the BRAM, the write address generator is connected to the write address port of the BRAM, and the write enabling generator is connected to the write enabling port of the BRAM; and
the read/write control signal generated by the read/write signal generation circuit comprises a read address generated by the read address generator, read enabling generated by the read enabling generator, a write address generated by the write address generator, and write enabling generated by the write enabling generator.

### Claim 14 (depends on 13)

The FPGA according to claim 13, wherein a plurality of BRAMs connected to the edge module form a full-chip storage array, the read/write controller in the edge module provides corresponding read enabling and write enabling for the plurality of BRAMs through the read/write signal generation circuit based on an obtained full-chip enabling signal, and the read/write controller in the edge module provides corresponding read address and write address for the plurality of BRAMs through the read/write signal generation circuit based on an obtained full-chip address signal.