# US 12,216,596 B2 · ZQ calibration circuit and method for memory interfaces

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- Number: US 12,216,596 B2
- Document ID: US12216596B2
- Status: Granted
- Kind: B2
- Application number: 17/941,790
- Filed: 2022-09-09
- Published: 2024-03-14
- Granted: 2025-02-04
- Earliest claimed: 2022-09-09
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Mohammad Reza Mahmoodi; Martin Lueker-Boden
- Web page: https://patentgrep.com/patent/US12216596B2

## CPC

- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 13/1673: {using buffers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods disclosed herein provide for an improved termination leg unit design and method of trimming impedance thereof, which provides for improved impedance matching for process variations, along with variations in temperature and voltage. Example implementation provide for a leg unit circuit design that includes a first circuit compensating for temperature and voltage variations and a second circuit, connected in series with the first circuit, compensating for process variations. Furthermore, disclosed herein is ZQ calibration method that provides for calibrating of the impedance of each of an on-die termination, a pull-up driver, and a pull-down driver using a single calibration circuit.

## Claims

### Claim 1

A termination leg unit circuit comprising:
a first circuit comprising a first plurality of switches configured to switchably connect a voltage supply to a data bus according to a target impedance between the voltage supply and the data bus; and
a second circuit connected in series between the first circuit and the data bus, the second circuit comprising a second plurality of switches configured to switchably connect a plurality of resistors between the first circuit and the data bus according to the target impedance, wherein the second circuit comprises a plurality of pairs, each pair comprising one of the second plurality of switches connected in parallel with one of the plurality of resistors.

### Claim 2 (depends on 1)

The termination leg unit circuit of claim 1, wherein the first plurality of switches are connected in parallel.

### Claim 3 (depends on 1)

The termination leg unit circuit of claim 1, further comprising a termination resistor connected between the data bus and the second circuit.

### Claim 4 (depends on 1)

The termination leg unit circuit of claim 1, further comprising a third circuit connected in parallel to the first circuit, the third circuit comprising a third at least one switch configured to reduce a dynamic range of the termination leg unit circuit.

### Claim 5 (depends on 1)

The termination leg unit circuit of claim 1, wherein the first plurality of switches and the second plurality of switches comprise p-channel metal-oxide-semiconductor field-effect transistors and the voltage supply is a high supply voltage.

### Claim 6 (depends on 1)

The termination leg unit circuit of claim 1, wherein the first plurality of switches and the second plurality of switches comprise n-channel metal-oxide-semiconductor field-effect transistors.

### Claim 7 (depends on 6)

The termination leg unit of claim 6, wherein the voltage supply is a low voltage supply.

### Claim 8

A memory device, the memory device comprising:
an on-chip calibration device coupled to a reference node;
a plurality of variable impedance circuits coupled to a plurality of nodes;
first circuitry configured to supply a reference voltage at the reference node based on a current in the on-chip calibration device;
second circuitry comprising a plurality of switches coupled to the plurality of nodes and configured to change the second circuitry between a plurality of configurations, the second circuitry configured to establish, for each configuration, a calibration voltage at one of the plurality of nodes based on current in one of plurality of variable impedance circuits connected to the respective one of the plurality of nodes;
a comparator circuit switchably connected to the reference node and the plurality of nodes and configured, for each configuration of the second circuitry, to compare the respective calibration voltage to the reference voltage; and
third circuitry configured to perform ZQ calibration for each configuration of the second circuitry, based on the comparison of the respective calibration to the reference voltage.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the on-chip calibration device is a resistor having a resistance value and a tolerance of ±1%.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the plurality of variable impedance circuits comprises an on-die termination (ODT) replica circuit having a variable resistance; a pull-up replica circuit having a variable resistance; and a pull-down replica circuit having a variable resistance.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the plurality of nodes comprises a first calibration node and a second calibration node, wherein the pull-down replica circuit is connected to the first calibration node and the ODT and the pull-up replica circuit are connected to the second calibration node.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein, in a first configuration of the plurality of configurations, the plurality of switches of the second circuitry pass current through the pull-down replica circuit, and the comparator circuit is connected to the reference node and the first calibration node, wherein the third circuitry calibrates the pull-down replica circuit based on the comparison of the calibration voltage at the first calibration node to the reference voltage.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein, in a second configuration of the plurality of configurations, the plurality of switches of the second circuitry pass current through the pull-up replica circuit, and the comparator circuit is connected to the reference node and the second calibration node, wherein the third circuitry calibrates the pull-up replica circuit based on the comparison of the calibration voltage at the second calibration node to the reference voltage.

### Claim 14 (depends on 11)

The memory device of claim 11, wherein, in a third configuration of the plurality of configurations, the plurality of switches of the second circuitry pass current through the ODT replica circuit, and the comparator circuit is connected to the reference node and the second calibration node, wherein the third circuitry calibrates the ODT replica circuit based on the comparison of the calibration voltage at the second calibration node to the reference voltage.

### Claim 15

A method comprising:
responsive to a ZQ calibration start command, activating a calibration circuitry and passing current from a first calibration node through a first variable impedance circuit of the calibration circuitry, wherein the calibration circuitry comprises an on-chip calibration device coupled to a reference node;
calibrating a first impedance value of the first variable impedance circuit based on a comparison of a first calibration voltage at the first calibration node to a reference voltage at the reference node;
responsive to a signal indicative that the calibration of the first impedance value is complete, disconnecting the first variable impedance circuit and passing current from a second calibration node through a second variable impedance circuit of the calibration circuitry;
calibrating a second impedance value of the second variable impedance circuit based on a comparison of a second calibration voltage at the second calibration node to a reference voltage at the reference node; and
responsive to a ZQ calibration latch command, latching the first impedance value into a first register of a first termination device and the second impedance value into a second register of a second termination device.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
responsive to a signal indicative that the calibration of the second impedance value is complete, disconnecting the second variable impedance circuit and passing current from the second calibration node through a third variable impedance circuit of the calibration circuitry;
calibrating a third impedance value of the third variable impedance circuit based on a comparison of a second calibration voltage at the second calibration node to a reference voltage at the reference node; and
responsive to the ZQ calibration latch command, latching the third impedance value into a third register of a third termination device.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first variable impedance circuit is a pull-down driver replica circuit, the second variable impedance circuit is a pull-up driver replica circuit, and the third variable impedance circuit is an on-die termination replica circuit.

### Claim 18 (depends on 15)

The method of claim 15, wherein the first variable impedance circuit comprises a plurality of leg unit circuits, each leg unit circuit comprising a first compensation circuit comprising a first plurality of switches and a second compensation circuit comprising a second plurality of switches, wherein calibrating the first impedance value comprises:
performing a coarse calibration on the second compensation circuit to determine switches of the second plurality of switches to activate; and
performing a fine calibration on the first compensation circuit to determine switches of the first plurality of switches to activate,
wherein the first impedance value comprises information indicative of which switches are determined to be activated.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first impedance value is a bit pattern comprising a first portion and a second portion, the first portion comprising binary values corresponding to the first plurality of switches, the second portion comprising binary values corresponding to the second plurality of switches.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first and second impedance values are a first and second ZQ calibration code corresponding to the first and second variable impedance circuits, respectively.