# US 12,216,591 B2 · Atomic compare and swap in a coherent cache system

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- Number: US 12,216,591 B2
- Document ID: US12216591B2
- Status: Granted
- Kind: B2
- Application number: 18/477,674
- Filed: 2023-09-29
- Published: 2024-01-25
- Granted: 2025-02-04
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen Bhoria; Timothy David Anderson; Pete Michael Hippleheuser
- Web page: https://patentgrep.com/patent/US12216591B2

## CPC

- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/12: Replacement control
- G06F 12/121: using replacement algorithms
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/127: using additional replacement algorithms
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1642: {with request queuing}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 15/8069: {using a cache}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/106: {Data output latches}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/72: {with optimized replacement algorithms}
- G11C 29/76: {using address translation or modifications}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1041: Resource optimization
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/301: In special purpose processing node, e.g. vector processor
- G06F 2212/454: Vector or matrix data
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G11C 29/4401: {for self repair}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

## Claims

### Claim 1

A device comprising:
a processor configured to:
receive a processor instruction; and
based on the processor instruction, provide a memory operation that specifies a value, an address, and a first set of data;
a cache controller coupled to the processor;
a tag memory coupled to the cache controller;
a store queue coupled to the cache controller; and
a first cache memory coupled to the store queue, wherein the cache controller is configured to, based on the memory operation:
determine whether the address is associated with a hit in the first cache memory;
based on the address being associated with a hit, determine whether to retrieve a second set of data from the first cache memory or a second cache memory based on a state stored in the tag memory and associated with the address; and
cause the store queue to:
determine whether the second set of data corresponds to the value; and
based on whether the second set of data corresponds to the value, determine whether to store the first set of data in the first cache memory.

### Claim 2 (depends on 1)

The device of claim 1, wherein the cache controller is configured to cause the store queue to replace the second set of data with the first set of data.

### Claim 3 (depends on 1)

The device of claim 1, wherein the cache controller is configured to, based on the address being associated with a miss in the first cache memory, retrieve the second set of data from the second cache memory.

### Claim 4 (depends on 1)

The device of claim 1, wherein the cache controller is configured to retrieve the second set of data from the second cache memory based on the address being associated with a hit and the state being a shared state.

### Claim 5 (depends on 4)

The device of claim 4, wherein the cache controller is configured to retrieve the second set of data from the first cache memory based on the address being associated with a hit and the state being a modified state or an exclusive state.

### Claim 6 (depends on 4)

The device of claim 4, wherein the cache controller is configured to retrieve the second set of data from the second cache memory by requesting the second set of data in an exclusive state.

### Claim 7 (depends on 6)

The device of claim 6, wherein the cache controller is configured to set the state stored in the tag memory to the exclusive state upon requesting the second set of data from the second cache memory.

### Claim 8 (depends on 6)

The device of claim 6, wherein the cache controller is configured to set the state stored in the tag memory to the exclusive state upon receiving the second set of data from the second cache memory.

### Claim 9 (depends on 1)

The device of claim 1, wherein the first cache memory is a level-one (L1) cache memory and the second cache memory is a level-two (L2) cache memory.

### Claim 10 (depends on 1)

The device of claim 1, wherein the first cache memory includes at least one of a main cache memory or a victim cache memory.

### Claim 11 (depends on 1)

The device of claim 1, wherein the store queue includes:
a compare circuit configured to:
determine whether the second set of data corresponds to the value; and
based on whether the second set of data corresponds to the value, determine whether to provide the first set of data for storing in the first cache memory at an output;
an arbitration manager coupled to the compare circuit and configured to store the first set of data in the first cache memory; and
a feedback path from the output of the compare circuit to an input of the compare circuit.

### Claim 12 (depends on 11)

The device of claim 11, wherein the store queue includes an arithmetic circuit coupled in parallel with the compare circuit.

### Claim 13 (depends on 11)

The device of claim 11, wherein the store queue includes a read-modify-write circuit coupled in parallel with the compare circuit.

### Claim 14

A method comprising:
receiving, by a cache controller, a memory operation that specifies a value, an address, and a first set of data;
determining whether the address is associated with a hit in a first cache memory;
based on the address being associated with a hit, determining whether to retrieve a second set of data associated with the address from the first cache memory or a second cache memory based on a state stored in a tag memory;
determining whether the second set of data corresponds to the value; and
determining whether to store the first set of data in the first cache memory based on whether the second set of data corresponds to the value.

### Claim 15 (depends on 14)

The method of claim 14 comprising, based on the second set of data corresponding to the value, replacing the second set of data with the first set of data.

### Claim 16 (depends on 14)

The method of claim 14 comprising retrieving the second set of data from the second cache memory based on the address being associated with a hit and the state being a shared state.

### Claim 17 (depends on 16)

The method of claim 16, wherein the retrieving of the second set of data from the second cache memory includes requesting the second set of data in an exclusive state.

### Claim 18 (depends on 14)

The method of claim 14 comprising retrieving the second set of data from the first cache memory based on the address being associated with a hit and the state being a modified state or an exclusive state.

### Claim 19 (depends on 14)

The method of claim 14, wherein the first cache memory is a level one (L1) cache memory and the second cache memory is a level two (L2) cache memory.

### Claim 20 (depends on 14)

The method of claim 14, wherein the first cache memory includes at least one of a main cache memory or a victim cache memory.