# US 12,216,587 B2 · Packet cache system and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,587 B2 - Document ID: US12216587B2 - Status: Granted - Kind: B2 - Application number: 18/583,341 - Filed: 2024-02-21 - Published: 2024-06-13 - Granted: 2025-02-04 - Earliest claimed: 2022-06-07 - Assignees: Google Inc. - Applicants: Google LLC - Inventors: Jiazhen Zheng; Srinivas Vaduvatha; Hugh McEvoy Walsh; Prashant R. Chandra; Abhishek Agarwal; Weihuang Wang; Weiwei Jiang - Web page: https://patentgrep.com/patent/US12216587B2 ## CPC - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0866: for peripheral storage systems, e.g. disk cache - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 12/121: using replacement algorithms - G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list - G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning - G06F 2212/1016: Performance improvement - G06F 2212/154: Networked environment - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high. ## Claims ### Claim 1 A packet cache system comprising: a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high; and a reorder engine for receiving a read request comprising a read address corresponding to the non-cache memory and allocated to a desired packet to be read from either the cache memory or the non-cache memory, and for storing the desired packet, upon reading from either the cache memory or the non-cache memory, into a reorder buffer such that the desired packet is supplied in response to the read request at a timing proper relative to a timing of other read requests. ### Claim 2 (depends on 1) The system according to claim 1, wherein the reorder engine is operable, upon receiving the read request, to assign a continuous space in the reorder buffer for accommodating the desired packet. ### Claim 3 (depends on 1) The system according to claim 1, further comprising a memory allocator for assigning the memory address to the packet. ### Claim 4 (depends on 3) The system according to claim 3, wherein the memory allocator is operable to form the packet into one or more cells, the one or more cells comprising a control cell when the packet is formed into one cell, and comprising a control cell and one or more data cells when the packet is formed into more than one cell, wherein the memory allocator assigns the memory address to the control cell, and respectively assigns one or more additional memory addresses to the one or more data cells. ### Claim 5 (depends on 4) The system according to claim 4, wherein when the packet is formed as more than one cell the control cell comprises one or more pointers to respective ones of the additional memory addresses. ### Claim 6 (depends on 4) The system according to claim 4, wherein when the packet is formed as more than one cell the cache memory allocator is operable to receive the one or more additional memory addresses and associate the one or more additional memory addresses with respective one or more additional cache memory addresses. ### Claim 7 (depends on 6) The system according to claim 6, wherein the hash table is operable to store the additional memory addresses and the additional cache memory addresses, with the additional memory addresses as keys and the additional cache memory addresses as respective values. ### Claim 8 (depends on 6) The system according to claim 6, wherein the cache memory is operable to store a portion of the packet at the location indicated by the cache memory address, and to store respective other portions of the packet at respective locations indicated by the additional cache memory addresses. ### Claim 9 (depends on 1) The system according to claim 1, wherein the eviction engine comprises a memory for storing a priority for each packet stored in the cache memory. ### Claim 10 (depends on 1) The system according to claim 1, wherein the system is an integral part of an integrated circuit. ### Claim 11 (depends on 10) The system according to claim 10, wherein the integrated circuit is an application-specific integrated circuit (ASIC). ### Claim 12 (depends on 10) The system according to claim 10, wherein the cache memory is an integral part of the integrated circuit, and the non-cache memory is external to the integrated circuit. ### Claim 13 (depends on 12) The system according to claim 12, wherein the cache memory is a static random-access memory (SRAM), and the non-cache memory is a dynamic random-access memory (DRAM). ### Claim 14 A method for storing packets in memory and reading the packets from memory, comprising: allocating a memory address, corresponding to a non-cache memory, to a packet; associating the memory address with a cache memory address; storing the memory address and the cache memory address in a hash table, with the memory address as a key and the cache memory address as a value; storing the packet in cache memory at a location indicated by the cache memory address; when occupancy of the cache memory is high, determining one or more cached packets to remove from the cache memory and place in the non-cache memory; receiving a read request comprising a read address corresponding to the non-cache memory and allocated to a desired packet to be read from either the cache memory or the non-cache memory; and storing the desired packet, upon reading from either the cache memory or the non-cache memory, into a reorder buffer such that the desired packet is supplied in response to the read request at a timing proper relative to a timing of other read requests. ### Claim 15 (depends on 14) The method according to claim 14, further comprising, upon receiving the read request, assigning a continuous space in the reorder buffer for accommodating the desired packet. ### Claim 16 (depends on 14) The method according to claim 14, wherein the step of allocating the memory address comprises: forming the packet into one or more cells, the one or more cells comprising a control cell when the packet is formed into one cell, and comprising a control cell and one or more data cells when the packet is formed into more than one cell; and allocating the memory address to the control cell, and respectively allocating one or more additional memory addresses to the one or more data cells. ### Claim 17 (depends on 16) The method according to claim 16 wherein when the packet is formed as more than one cell the control cell comprises one or more pointers to respective ones of the additional memory addresses. ### Claim 18 (depends on 16) The method according to claim 16, wherein when the packet is formed as more than one cell the method further comprises associating the one or more additional memory addresses with respective one or more additional cache memory addresses. ### Claim 19 (depends on 18) The method according to claim 18, wherein the step of storing the memory address and the cache memory address in the hash table further comprises storing the additional memory addresses and the additional cache memory addresses in the hash table, with the additional memory addresses as keys and the additional cache memory addresses as respective values. ### Claim 20 (depends on 19) The method according to claim 19, wherein the step of storing the packet in cache memory at a location comprises storing a portion of the packet at the location indicated by the cache memory address, and storing respective other portions of the packet at respective locations indicated by the additional cache memory addresses.