# US 12,216,585 B2 · Coherent memory access > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,585 B2 - Document ID: US12216585B2 - Status: Granted - Kind: B2 - Application number: 18/129,559 - Filed: 2023-03-31 - Published: 2024-09-05 - Granted: 2025-02-04 - Earliest claimed: 2018-10-10 - Applicants: Lodestar Licensing Group LLC - Inventors: Timothy P. Finkbeiner; Troy D. Larsen - Web page: https://patentgrep.com/patent/US12216585B2 ## CPC - G06F 12/0815: Cache consistency protocols - G06F 12/0877: Cache access modes - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 2212/221: Static RAM - G06F 2212/656: Address space sharing - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address. ## Claims ### Claim 1 An apparatus, comprising: a first cache line and a second cache line coupled to a memory array; a first cache controller coupled to a first processing resource and to the first cache line and configured to provide coherent access to data stored in the second cache line and corresponding to a memory address; and a second cache controller coupled through an interface to a second processing resource and coupled to the second cache line and configured to provide coherent access to data stored in the first cache line and corresponding to the memory address, wherein coherent access is provided by, responsive to determining that the memory address is stored in a cache line address register of the first cache controller, locking the first cache line prior to copying the data from the first cache line to the second cache line. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first cache line is locked to prevent the first cache line from being written to or read. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the apparatus is further configured to receive, from a host, an access request utilizing the interface that is used to synchronize a memory device and the host. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the interface synchronizes the host and the memory device using a timing bus coupling the memory device to the host. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein coherent access is provided by, responsive to determining that the memory address is stored in a cache line address register of the second cache controller, locking the second cache line prior to copying the data from the first cache line to the second cache line. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the first cache controller is further configured to request a transfer of the data stored in the second cache line to the first cache line from an abstract state machine (ASM) of the apparatus. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the ASM is coupled to the first cache controller and the second cache controller. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the first cache controller is further configured to request a direct transfer of the data stored in the second cache line, wherein the data stored in the second cache line is directly transferred from the second cache line to the first cache line. ### Claim 9 A method for providing coherent data, comprising: receiving, at a first cache controller of a memory device, an access command requesting data from a memory address; determining whether the memory address is associated with a first cache line corresponding to the first cache controller by referencing a first cache line address register; responsive to determining that the memory address is not associated with the first cache line, determining whether the memory address is associated with a second cache line corresponding to a second cache controller by referencing a second cache line address register; responsive to determining that the memory address is stored in the second cache line and that the first cache line is populated, flushing first data stored in the first cache line; and responsive to determining that the memory address is stored in the second cache line address register: locking the second cache line; and copying the requested data from the second cache line to the first cache line to provide data coherency between the first cache line and the second cache line. ### Claim 10 (depends on 9) The method of claim 9, wherein the first data is flushed by storing the first data to an array prior to copying the requested data to the first cache line. ### Claim 11 (depends on 9) The method of claim 9, wherein determining whether the memory address is associated with the first cache line further comprises determining whether a value stored in the first cache line address register of the first cache controller is equal to the memory address. ### Claim 12 (depends on 11) The method of claim 11, further comprising, responsive to determining that the value stored in the first cache line address register is equal to the memory address, responding to the access command by providing the requested data stored in the first cache line via a stream interconnect without relying on a timing component. ### Claim 13 (depends on 9) The method of claim 9, further comprising, responsive to locking the second cache line, requesting a copying of the requested data stored in the second cache line from an abstract state machine (ASM), wherein the copying is a direct transfer of the requested data from the second cache line to the first cache line. ### Claim 14 (depends on 9) The method of claim 9, further comprising, responsive to transferring the requested data to the first cache line, unlocking the second cache line. ### Claim 15 An apparatus, comprising: a first cache line and a second cache line coupled to a memory array; a first cache controller coupled to a first processing resource and to the first cache line and configured to provide coherent access to data stored in the second cache line and corresponding to a memory address; and a second cache controller coupled to a second processing resource and coupled to the second cache line and configured to provide coherent access to data stored in the first cache line and corresponding to the memory address, wherein coherent access is provided by, responsive to determining that the memory address is stored in a first cache line address register of the first cache controller and a second cache line address register of the second cache controller: storing write data received with a write command in the first cache line; and providing an invalidation command to the second cache controller to invalidate the second cache line, wherein the invalidation command is provided from the first cache controller to the second cache controller. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein coherent access is provided by, responsive to providing the invalidation command, copying the write data from the first cache line to the second cache line. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the invalidation command is provided to the second cache controller to invalidate the data stored in the second cache line. ### Claim 18 (depends on 15) The apparatus of claim 15, wherein the second cache controller is coupled to the second processing resource via an interface. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the first processing resource and the second processing resource are in different banks. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the second processing resource and the first processing resource are in a same bank.