# US 12,216,581 B2 · System, method, and apparatus for enhanced pointer identification and prefetching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,581 B2 - Document ID: US12216581B2 - Status: Granted - Kind: B2 - Application number: 18/320,780 - Filed: 2023-05-19 - Published: 2023-12-21 - Granted: 2025-02-04 - Earliest claimed: 2018-12-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Sreenivas Subramoney; Stanislav Shwartsman; Anant Nori; Shankar Balachandran; Elad Shtiegmann; Vineeth Mekkat; Manjunath Shevgoor; Sourabh Alurkar - Web page: https://patentgrep.com/patent/US12216581B2 ## CPC - G06F 12/0862: with prefetch - G06F 12/0811: with multilevel cache hierarchies - G06F 2212/1024: Latency reduction - G06F 2212/507: using speculative control - G06F 2212/602: Details relating to cache prefetching - G06F 2212/6024: History based prefetching - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data. ## Claims ### Claim 1 An apparatus comprising: predictor circuitry to detect a pointer load instruction to load a pointer based, at least in part, on one or more previously executed pointer load instructions, wherein the one or more previously executed pointer load instructions caused access to a second memory address satisfying a condition relative to a first memory address identified by the pointer load instruction; and prefetcher circuitry to detect an upcoming execution of the pointer load instruction and to prefetch the pointer at the first memory address and data for a next data load instruction, the next data load instruction associated with the pointer load instruction, wherein a location of the data is identified based on the pointer. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the condition corresponds to a match between the first and second memory addresses. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the condition corresponds to the first and second memory addresses being stored within a common cache line. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising storage circuitry to track a number of previously executed data load instructions associated with the pointer load instruction. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein a counter of the storage circuitry is incremented for each previously executed data load instruction associated with the pointer load instruction. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the predictor circuitry is to identify the pointer load instruction as a data load instruction when a counter value of the counter exceeds a specified threshold. ### Claim 7 (depends on 5) The apparatus of claim 5, further comprising a timer to track clock cycles and wherein the counter is decremented after each specified number of clock cycles. ### Claim 8 A method comprising: detecting a pointer load instruction to load a pointer based, at least in part, on one or more previously executed pointer load instructions, wherein the one or more previously executed pointer load instructions caused access to a second memory address satisfying a condition relative to a first memory address identified by the pointer load instruction; detecting an upcoming execution of the pointer load instruction; and prefetching the pointer at the first memory address and data for a next data load instruction, the next data load instruction associated with the pointer load instruction, wherein a location of the data is identified based on the pointer. ### Claim 9 (depends on 8) The method of claim 8, wherein the condition corresponds to a match between the first and second memory addresses. ### Claim 10 (depends on 8) The method of claim 8, wherein the condition corresponds to the first and second memory addresses being stored within a common cache line. ### Claim 11 (depends on 8) The method of claim 8, further comprising: tracking, by a storage circuitry, a number of previously executed data load instructions associated with the pointer load instruction. ### Claim 12 (depends on 11) The method of claim 11, wherein a counter of the storage circuitry is incremented for each previously executed data load instruction associated with the pointer load instruction. ### Claim 13 (depends on 12) The method of claim 12, wherein detecting the pointer load instruction comprises identifying the pointer load instruction as a data load instruction when a counter value of the counter exceeds a specified threshold. ### Claim 14 A system comprising: memory to store instructions; predictor circuitry to detect a pointer load instruction to load a pointer based, at least in part, on one or more previously executed pointer load instructions, wherein the one or more previously executed pointer load instructions caused access to a second memory address satisfying a condition relative to a first memory address identified by the pointer load instruction; and prefetcher circuitry to detect an upcoming execution of the pointer load instruction and to prefetch the pointer at the first memory address and data for a next data load instruction, the next data load instruction associated with the pointer load instruction, wherein a location of the data is identified based on the pointer. ### Claim 15 (depends on 14) The system of claim 14, wherein the condition corresponds to a match between the first and second memory addresses. ### Claim 16 (depends on 14) The system of claim 14, wherein the condition corresponds to the first and second memory addresses being stored within a common cache line. ### Claim 17 (depends on 14) The system of claim 14, further comprising storage circuitry to track a number of previously executed data load instructions associated with the pointer load instruction. ### Claim 18 (depends on 17) The system of claim 17, wherein a counter of the storage circuitry is incremented for each previously executed data load instruction associated with the pointer load instruction. ### Claim 19 (depends on 18) The system of claim 18, wherein the predictor circuitry is to identify the pointer load instruction as a data load instruction when a counter value of the counter exceeds a specified threshold. ### Claim 20 (depends on 18) The system of claim 18, further comprising a timer to track clock cycles and wherein the counter is decremented after each specified number of clock cycles.