# US 12,216,573 B2 · Memory device with dynamic cache management

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- Number: US 12,216,573 B2
- Document ID: US12216573B2
- Status: Granted
- Kind: B2
- Application number: 18/395,363
- Filed: 2023-12-22
- Published: 2024-04-18
- Granted: 2025-02-04
- Earliest claimed: 2017-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kishore Kumar Muchherla; Peter Feeley; Ashutosh Malshe; Daniel J. Hubbard; Christopher S. Hale; Kevin R. Brandt; Sampath K. Ratnam; Yun Li; Marc S. Hamilton
- Web page: https://patentgrep.com/patent/US12216573B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/064: {Management of blocks}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 3/0689: {Disk arrays, e.g. RAID, JBOD}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G06F 12/0646: {Configuration or reconfiguration}
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/2022: Flash memory
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

## Claims

### Claim 1

An apparatus, comprising:
a memory array including memory cells; and
a controller coupled to the memory array, the controller configured to:
designate a portion of the memory cells as cache memory;
designate a storage mode for the cache memory based on a data storage measure,
wherein the storage mode is for dynamically configuring the cache memory to store a number of bits less per cell than a maximum capacity of bits per cell.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the data storage measure is correlated with valid data stored in the cache memory.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the valid data is associated with a garbage collection (GC) process.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the controller is configured to designate single-level cell (SLC) mode for the storage mode when the valid data associated with the GC process is below a decision threshold.

### Claim 5 (depends on 3)

The apparatus of claim 3 wherein the controller is configured to designate an extra-level cell (XLC) mode for the storage mode when the valid data is not less than a decision threshold.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein:
the cache memory is associated with a GC source block; and
the controller is further configured to:
calculate the data storage measure for the GC source block for representing an amount of the valid data within the GC source block; and
designate the cache memory to operate in SLC mode based on comparing the data storage measure to a decision threshold.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the decision threshold corresponds to operating the cache memory in the SLC mode when the valid data within the source block is less than 25% of a total capacity of the source block.

### Claim 8 (depends on 1)

The apparatus of claim 1 wherein the cache memory is indicated by a host cursor for the subsequent or upcoming data writes.

### Claim 9 (depends on 1)

The apparatus of claim 1 wherein the cache memory is indicated by a GC cursor for the subsequent or upcoming data writes.

### Claim 10 (depends on 1)

The apparatus of claim 1 wherein the controller is further configured to:
according to the data storage measure, determine a low logic saturation state for the memory array; and
based on the low logic saturation state, designate SLC mode for the storage mode for upcoming data writes.

### Claim 11 (depends on 1)

The apparatus of claim 1 wherein the controller is configured to designate the storage mode as SLC mode under steady-state.

### Claim 12 (depends on 1)

The apparatus of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of an amount of the data previously written in the SLC mode.

### Claim 13 (depends on 1)

The apparatus of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of a data desirability measure associated with a performance model for characterizing the previously stored data.

### Claim 14

A method of operating an apparatus that includes a controller and memory array having memory cells, the method comprising:
designating a portion of the memory cells as cache memory;
designating a storage mode for the cache memory based on a data storage measure,
wherein the storage mode is for dynamically configuring the cache memory to store a number of bits per cell less than the corresponding maximum storage capacity.

### Claim 15 (depends on 14)

The method of claim 14, wherein the data storage measure is correlated with valid data stored in the cache memory.

### Claim 16 (depends on 15)

The method of claim 15, wherein the valid data is identified during a GC process.

### Claim 17 (depends on 14)

The method of claim 14, wherein the cache memory is indicated by a GC cursor for a subsequent or upcoming data writes.

### Claim 18 (depends on 14)

The method of claim 14, wherein designating the storage mode includes designating a SLC mode for the storage mode when the valid data is less than a decision threshold.

### Claim 19 (depends on 18)

The method of claim 18, wherein designating the SLC mode includes designating the SLC mode regardless of an amount of the data previously written in the SLC mode, regardless of a data desirability measure associated with a performance model for characterizing the previously stored data, or a combination thereof.

### Claim 20

A memory system, comprising:
a host device; and
a memory device coupled to the host device and configured to store data and provide access to the data for the host device, the memory device further configured to:
designate a portion of local storage capacity as cache memory;
designate a storage mode for the cache memory based on a data storage measure,
wherein the storage mode is for dynamically configuring the cache memory to store a number of bits less per cell than a maximum capacity of bits per cell.