# US 12,216,572 B2 · Atomic write operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,572 B2 - Document ID: US12216572B2 - Status: Granted - Kind: B2 - Application number: 18/591,942 - Filed: 2024-02-29 - Published: 2024-08-22 - Granted: 2025-02-04 - Earliest claimed: 2022-05-12 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Giuseppe Cariello - Web page: https://patentgrep.com/patent/US12216572B2 ## CPC - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 3/061: {Improving I/O performance} - G06F 3/064: {Management of blocks} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 2212/1024: Latency reduction - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses. ## Claims ### Claim 1 A method comprising: receiving, at a host system, a sequence of data comprising first data and second data from a same application of the host system; transmitting, by the host system based at least in part on the first data and the second data being from the same application, a write command that indicates a first set of logical addresses for the first data and a second set of logical addresses for the second data and that indicates the first data and the second data are included in the sequence of data; writing, by a memory system to a non-volatile memory, the first data and the second data based at least in part on receiving the write command transmitted by the host system; and writing, by the memory system to the non-volatile memory, first metadata for the first data and second metadata for the second data based at least in part on the write command indicating the first data and the second data are included in the sequence of data, wherein the first metadata indicates that the first data is included in the sequence of data and the second metadata indicates that the second data is included in the sequence of data. ### Claim 2 (depends on 1) The method of claim 1, wherein the write command indicates that the memory system is to track a storage status of the sequence of data. ### Claim 3 (depends on 1) The method of claim 1, further comprising: receive, at the host system, an indication that the second data is a last set of data for the sequence of data, wherein transmission of the write command is delayed until after the host system receives the indication that the second data is the last set of data for the sequence of data. ### Claim 4 (depends on 1) The method of claim 1, further comprising: transmitting, by the memory system based at least in part on receiving the write command, a first request for the first data and a second request for the second data, wherein the first data and the second data are received based at least in part on transmitting the first request and the second request. ### Claim 5 (depends on 1) The method of claim 1, wherein the write command indicates a starting logical address for the first set of logical addresses and a quantity of the first set of logical addresses, and wherein the write command further indicates a starting logical address for the second set of logical addresses and a quantity of the second set of logical addresses. ### Claim 6 (depends on 5) The method of claim 5, further comprising: determining, by the memory system, the first set of logical addresses based at least in part on the starting logical address for the first set of logical addresses and on the quantity of the first set of logical addresses; and determining, by the memory system, the second set of logical addresses based at least in part on the starting logical address for the second set of logical addresses and on the quantity of the second set of logical addresses. ### Claim 7 (depends on 1) The method of claim 1, wherein the write command indicates a starting logical address for the first set of logical addresses, a quantity of the first set of logical addresses, a difference between the starting logical address for the first set of logical addresses and a starting address for the second set of logical addresses, and a quantity of the second set of logical addresses. ### Claim 8 (depends on 7) The method of claim 7, further comprising: determining, by the memory system, the first set of logical addresses based at least in part on the starting logical address for the first set of logical addresses and the quantity of the first set of logical addresses; and determining, by the memory system, the second set of logical addresses based at least in part on the starting logical address for the first set of logical addresses, the difference, and the quantity of the second set of logical addresses. ### Claim 9 (depends on 1) The method of claim 1, wherein the first set of logical addresses is contiguous, the second set of logical addresses is contiguous, and the write command indicates that the first set of logical addresses is discontiguous with the second set of logical addresses. ### Claim 10 (depends on 1) The method of claim 1, further comprising: determining, by the memory system based at least in part on a failure event, a storage status of the sequence of data based at least in part on the first metadata and the second metadata. ### Claim 11 (depends on 10) The method of claim 10, further comprising: discarding, by the memory system, a subset of the sequence of data based at least in part on the storage status indicating that only the subset of the sequence of data has been written to the non-volatile memory. ### Claim 12 (depends on 1) The method of claim 1, wherein the first metadata is written to a same first set of pages as the first data, and wherein the second metadata is written to a same second set of pages page as the second data. ### Claim 13 (depends on 1) The method of claim 1, further comprising: determining, by the memory system based at least in part on the write command, whether the second data is a last set of data included in the sequence of data, wherein the second metadata comprises an indication that the second data is the last set of data. ### Claim 14 A method, comprising: transmitting, by a host system, a command for a memory system to enter a mode for receiving a sequence of data; transmitting, by the host system based at least in part on transmitting the command, a write command for a set of data included in the sequence of data, the write command comprising an identifier equal to a value associated with the mode; writing, by the memory system to a non-volatile memory, the set of data based at least in part on the write command; and writing, by the memory system to the non-volatile memory, metadata for the set of data based at least in part on the identifier of the write command being equal to the value associated with the mode, wherein the metadata indicates that the set of data is included in the sequence of data. ### Claim 15 (depends on 14) The method of claim 14, further comprising: determining whether the set of data is included in the sequence of data based at least in part on the identifier being equal to the value associated with the mode. ### Claim 16 (depends on 14) The method of claim 14, further comprising: determining, by the memory system based at least in part on a failure event, whether only a subset of the sequence of data has been written to the non-volatile memory based at least in part on the metadata; and discarding, by the memory system, the subset of the sequence of data based at least in part on determining that only the subset has been written. ### Claim 17 (depends on 14) The method of claim 14, further comprising: determining, by the memory system based at least in part on the write command, whether the set of data is a last set of data for the sequence of data, wherein the metadata comprises an indication that the set of data is the last set of data for the sequence of data. ### Claim 18 (depends on 14) The method of claim 14, further comprising: determining, by the memory system, whether the set of data is a first set of data for the sequence of data, wherein the metadata comprises an indication that the set of data is the first set of data for the sequence of data. ### Claim 19 (depends on 14) The method of claim 14, further comprising: receiving, from the host system after writing the set of data to the non-volatile memory, a second command to exit the mode for receiving the sequence of data, wherein the second command is received before receipt of a last write command for the sequence of data. ### Claim 20 An apparatus, comprising: one or more memory system controllers of a memory system that comprises one or more non-volatile memory devices; and one or more host system controllers of a host system coupled with the memory system, wherein the one or more host system controllers is configured to cause the host system to: receive a sequence of data comprising first data and second data from a same application of the host system; transmit, based at least in part on the first data and the second data being from the same application, a write command that indicates a first set of logical addresses for the first data and a second set of logical addresses for the second data and that indicates the first data and the second data are included in the sequence of data; and wherein the one or more memory system controllers is configured to cause the memory system to: write, to the one or more non-volatile memory devices, the first data and the second data based at least in part on receiving the write command; and write, to the one or more non-volatile memory devices, first metadata for the first data and second metadata for the second data based at least in part on the write command indicating the first data and the second data are included in the sequence of data, wherein the first metadata indicates that the first data is included in the sequence of data and the second metadata indicates that the second data is included in the sequence of data.