# US 12,216,571 B2 · Storage device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,571 B2 - Document ID: US12216571B2 - Status: Granted - Kind: B2 - Application number: 18/486,163 - Filed: 2023-10-13 - Published: 2024-02-01 - Granted: 2025-02-04 - Earliest claimed: 2021-07-13 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Byung Jun Kim; Jea Young Zhang; Young Kyu Jeon; Kyoung Ku Cho - Web page: https://patentgrep.com/patent/US12216571B2 ## CPC - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 3/061: {Improving I/O performance} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0607: {Interleaved addressing} - G06F 2212/1016: Performance improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses. ## Claims ### Claim 1 A storage device comprising: a memory device; and a memory controller configured to receive a write command from an external host and control the memory device according to the write command, wherein the write command comprises: a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the write command is a command for requesting to data in the memory device; a transaction specific field including information indicating that the write command is a write command for at least two or more logical addresses; and an extra header segment including information on the at least two or more logical addresses. ### Claim 2 (depends on 1) The storage device of claim 1, wherein the information on the at least two or more logical addresses includes information on at least two start logical block addresses and transfer lengths respectively corresponding to the at least two or more start logical block addresses. ### Claim 3 (depends on 1) The storage device of claim 1, wherein the at least two or more logical addresses are not successive with each other. ### Claim 4 (depends on 1) The storage device of claim 1, wherein the transaction specific field includes a write command descriptor block (CDB). ### Claim 5 (depends on 4) The storage device of claim 4, wherein the write CDB includes the information indicating that the write command is the write command for the at least two or more logical addresses. ### Claim 6 (depends on 5) The storage device of claim 5, wherein the information indicating that the write command is the write command for the at least two or more logical addresses is included in a reserved field in the write CDB. ### Claim 7 (depends on 6) The storage device of claim 6, wherein the write CDB further includes operation code field, a force unit access field, and a group number field. ### Claim 8 (depends on 1) The storage device of claim 1, wherein the basic header segment includes a total extra header segment length field indicating a length of the extra header segment. ### Claim 9 (depends on 8) The storage device of claim 8, wherein the total extra header segment length field includes a non-zero value. ### Claim 10 A method of operating a storage device including a memory device and a memory controller that controls the memory device, the method comprising: receiving, from an external host, a write command including: a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the write command is a command for requesting to store data in the memory device, a transaction specific field including information indicating that the write command is a write command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses; and performing a write operation based on the information on the at least two or more logical addresses. ### Claim 11 (depends on 10) The method of claim 10, wherein the information on the at least two or more logical addresses includes information on at least two start logical block addresses and transfer lengths respectively corresponding to the at least two or more start logical block addresses. ### Claim 12 (depends on 10) The method of claim 10, wherein the basic header segment includes a total extra header segment length field indicating a length of the extra header segment. ### Claim 13 (depends on 12) The method of claim 12, wherein the total extra header segment length field includes a non-zero value. ### Claim 14 (depends on 10) The method of claim 10, wherein the at least two or more logical addresses are not successive with each other. ### Claim 15 (depends on 10) The method of claim 10, wherein the transaction specific field includes a write command descriptor block (CDB). ### Claim 16 (depends on 15) The method of claim 15, wherein the write CDB includes the information indicating that the write command is the write command for the at least two or more logical addresses. ### Claim 17 (depends on 16) The method of claim 16, wherein the information indicating that the write command is the write command for the at least two or more logical addresses is included in a reserved field in the write CDB. ### Claim 18 (depends on 10) The method of claim 10, further comprising receiving data, from the external host, to be stored in locations corresponding the at least two or more logical addresses. ### Claim 19 (depends on 18) The method of claim 18, wherein the data is stored in the memory device according to an order of logical block address information included in the extra header segment. ### Claim 20 A memory controller that controls a memory device, the memory controller comprising: a map data storage configured to store mapping information between a logical address and a physical address of data stored in the memory device; a request processor configured to receive a write request from an external host and obtain physical addresses corresponding to at least one or more logical addresses included in the write request; and an operation controller configured to provide the memory device with a command for the physical addresses corresponding to the at least one or more logical addresses to, wherein the request comprises: a basic header segment commonly included in requests transmitted and received between the external host and the memory controller and including information indicating that the write request is for requesting to store data in the memory device; a transaction specific field including information indicating that the write request is a write request for at least two or more logical addresses; and an extra header segment including information on the at least two or more logical addresses.