# US 12,216,566 B2 · Debug operations on artificial intelligence operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,566 B2 - Document ID: US12216566B2 - Status: Granted - Kind: B2 - Application number: 17/953,130 - Filed: 2022-09-26 - Published: 2023-01-19 - Granted: 2025-02-04 - Earliest claimed: 2019-08-28 - Applicants: Lodestar Licensing Group LLC - Inventors: Alberto Troia - Web page: https://patentgrep.com/patent/US12216566B2 ## CPC - G06F 11/364: {tracing values on a bus} - G06F 11/0775: {Content or structure details of the error report, e.g. specific table structure, specific error fields} - G06F 11/0778: {Dumping, i.e. gathering error/state information after a fault for later diagnosis} - G06F 11/0787: {Storage of error reports, e.g. persistent data storage, storage using memory protection} - G06F 13/1668: {Details of memory controller} - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/048: Activation functions - G06N 3/0499: Feedforward networks - G06N 3/063: using electronic means - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract The present disclosure includes apparatuses and methods related to performing a debug operation on an artificial intelligence operation. An example apparatus can include a number of memory arrays and a controller, wherein the controller is configured to perform an artificial intelligence (AI) operation on data stored in the number of memory arrays and perform a debug operation on the AI operation. ## Claims ### Claim 1 An apparatus, comprising: an artificial intelligence (AI) accelerator; a number of memory arrays coupled to the AI accelerator; a number of registers coupled to the AI accelerator; and a controller coupled to the AI accelerator, wherein the controller is configured to: perform an AI operation via the AI accelerator using at least one of: activation function data, partial results of AI operations, or bias value data; store a location of a layer of a neural network where an error occurred during the AI operation in a first register of the number of registers in response to the error occurring; stop the AI operation at the layer of the neural network where the error occurred in response to a particular bit of a second register of the number of registers being programmed to a particular state; and perform a debug operation on the AI operation in response to a particular bit of a third register of the number of registers being programmed to a particular state. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is configured to perform the AI operation on data stored in the number of memory arrays. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the controller is configured to perform the debug operation to identify errors of the AI operation. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the controller is configured to store data in a temporary memory block of the number of memory arrays in response to a particular bit of a fourth register being programmed to a particular state. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the data includes identified errors from the debug operation. ### Claim 6 An apparatus, comprising: an artificial intelligence (AI) accelerator; a number of memory arrays coupled to the AI accelerator; a number of registers coupled to the AI accelerator; and a controller coupled to the AI accelerator, wherein the controller is configured to: perform an AI operation via the AI accelerator using at least one of: activation function data, partial results of AI operations, or bias value data; store a location of a layer of a neural network where an error occurred during the AI operation in a first register of the number of registers in response to the error occurring; stop the AI operation at the layer of the neural network where the error occurred; perform a debug operation on the AI operation to identify errors of the AI operation in response to a particular bit of a second register of the number of registers being programmed to a particular state; store data in a temporary memory block of the number of memory arrays in response to a particular bit of a third register of the number of registers being programmed to a particular state; and change the data stored in the temporary memory block to correct the identified errors. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the controller is configured to stop the AI operation in response to a different bit of the second register of the number of registers being programmed to a particular state. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the controller is configured to continue the AI operation in response to the different bit of the second register being programmed to a different state. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the controller is configured to continue the AI operation with the changed data. ### Claim 10 (depends on 6) The apparatus of claim 6, wherein the controller is configured to validate the temporary memory block. ### Claim 11 (depends on 6) The apparatus of claim 6, wherein the controller is configured to send a result of the debug operation. ### Claim 12 A method, comprising: receiving a debug command from a host; programming a particular bit of a first register of a number of registers to a particular state in response to receiving the debug command from the host; performing an artificial intelligence (AI) operation via an AI accelerator coupled to the number of registers using at least one of: activation function data, partial results of AI operations, or bias value data; storing a location of a layer of a neural network where an error occurred during the AI operation in a second register of the number of registers in response to the error occurring; stopping the AI operation at the layer of the neural network where the error occurred; performing a debug operation on the AI operation in response to the particular bit of the first register being programmed to the particular state; programming a particular bit of a third register of the number of registers to a particular state; and storing data in a temporary memory block in response to the particular bit of the third register being programmed to the particular state. ### Claim 13 (depends on 12) The method of claim 12, comprising performing the AI operation on data stored in a number of memory arrays. ### Claim 14 (depends on 13) The method of claim 13, comprising performing the AI operation using at least one of: input data or neural network data. ### Claim 15 (depends on 12) The method of claim 12, comprising programming a different bit of the first register to a different state. ### Claim 16 (depends on 15) The method of claim 15, comprising indicating the AI operation is to step forward to continue the AI operation in response to programming the different bit of the first register to the different state. ### Claim 17 (depends on 15) The method of claim 15, comprising indicating the temporary block is valid in response to programming the different bit of the first register to the different state. ### Claim 18 (depends on 15) The method of claim 15, comprising storing a result of the debug operation in response to programming the different bit of the first register to the different state. ### Claim 19 (depends on 15) The method of claim 15, comprising sending a result of the debug operation in response to programming the different bit of the first register to the different state.