# US 12,216,553 B2 · Flash memory architecture implementing interconnection redundancy > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,553 B2 - Document ID: US12216553B2 - Status: Granted - Kind: B2 - Application number: 18/535,899 - Filed: 2023-12-11 - Published: 2024-08-01 - Granted: 2025-02-04 - Earliest claimed: 2022-09-29 - Applicants: Lodestar Licensing Group LLC - Inventors: Alberto Troia; Antonino Mondello - Web page: https://patentgrep.com/patent/US12216553B2 ## CPC - G06F 11/201: {between storage system components} - G11C 29/702: {by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones} - G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)} - G06F 11/1666: {where the redundant component is memory or memory area} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/789: {using non-volatile cells or latches} - G11C 29/835: {with roll call arrangements for redundant substitutions} - G11C 29/846: {by choosing redundant lines at an output stage} - G06F 2201/85: Active fault masking without idle spares - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 29/022: {in I/O circuitry} - G11C 29/025: {in signal lines} - G11C 2029/0401: {in embedded memories} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed. ## Claims ### Claim 1 A memory device, comprising: a register coupled to a first plurality of connection pads and a second plurality of connection pads; and control circuitry coupled to the register and configured to: substitute an original pad address of a first page of the register with a redundant pad address of the first page of the register; and substitute an original pad address of a second page of the register with a redundant pad address of the second page of the register, wherein a redundancy associated with the redundant pad address of the first page or the redundant pad address of the second page is either a single-pad redundancy or a multi-pad redundancy. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the memory device comprises a selection circuit connected to the register, the first plurality of pads, and at least one connection pad of the second plurality of connection pads. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the selection circuit is configured to implement an interconnection redundancy involving the first plurality of connection pads and the second plurality of connection pads. ### Claim 4 (depends on 2) The memory device of claim 2, wherein the selection circuit comprises: a first switch inserted between a plurality of data lines and one of the first plurality of connection pads; and a second switch inserted between the plurality of data lines and at least one of the second plurality of connection pads. ### Claim 5 (depends on 4) The memory device of claim 4, wherein the selection circuit comprises: a first logic gate to receive a first redundant signal associated with a flag stored in a first portion of the register to command the first switch; and a second logic gate to receive the first redundant signal and a second redundant signal associated with an address stored in a second portion of the register to command the second switch. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the register includes a first portion, a second portion, and a third portion. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the first portion of the register comprises a redundant flag that indicates a usage of the redundancy. ### Claim 8 (depends on 6) The memory device of claim 6, wherein the second portion of the register stores an address of a defective connection pad. ### Claim 9 (depends on 6) The memory device of claim 6, wherein the third portion of the register stores an address of a spare connection pad. ### Claim 10 (depends on 1) The memory device of claim 1, wherein a second portion of a single-pad redundancy stores one address and a second portion of the multi-pad redundancy stores a plurality of addresses. ### Claim 11 A method, comprising: determining that a connection pad of a first plurality of connection pads is not functioning properly; coupling the connection pad of the first plurality of connection pads to a connection pad of a second plurality of connection pads by: substituting an original pad address of a first page of a register with a redundant pad address of the first page of the register; and substituting an original pad address of a second page of the register with a redundant pad address of the second page of the register; programming a first type of redundancy using a first memory component; and programming a second type of redundancy using a second memory component. ### Claim 12 (depends on 11) The method of claim 11, further comprising making the determination that the connection pad of the first plurality of connection pads is not functioning properly based on information associated with the register. ### Claim 13 (depends on 11) The method of claim 11, further comprising coupling the connection pad of the first plurality of connection pads to a connection pad of a second plurality of connection pads via data lines. ### Claim 14 An apparatus, comprising: a plurality of subarrays of memory cells; a register coupled to a first plurality of connection pads, a second plurality of connection pads, and control circuitry; the control circuitry configured to: substitute an original pad address of a first page of the register with a redundant pad address of the first page of the register; and substitute an original pad address of a second page of the register with a redundant pad address of the second page of the register, wherein a redundancy associated with the redundant pad address of the first page or the redundant pad address of the second page is either a single-pad redundancy or a multi-pad redundancy. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the first plurality of connection pads corresponds to channels of the plurality of subarrays of memory cells. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the second plurality of connection pads is coupled to the first plurality of connection pads. ### Claim 17 (depends on 14) The apparatus of claim 14, wherein the register comprises a first page coupled to the first plurality of connection pads and a second page coupled to the second plurality of connection pads. ### Claim 18 (depends on 14) The apparatus of claim 14, wherein an interconnection redundancy is replicated each of the plurality of subarrays of memory cells.