# US 12,216,543 B2 · Fault tolerant memory systems and components with interconnected and redundant data interfaces

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- Number: US 12,216,543 B2
- Document ID: US12216543B2
- Status: Granted
- Kind: B2
- Application number: 18/203,576
- Filed: 2023-05-30
- Published: 2023-11-09
- Granted: 2025-02-04
- Earliest claimed: 2015-09-28
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Kenneth L. Wright; Frederick A. Ware
- Web page: https://patentgrep.com/patent/US12216543B2

## CPC

- G06F 11/142: {Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044)}
- G06F 3/0617: {in relation to availability}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0683: {Plurality of storage devices}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 13/1673: {using buffers}
- G06F 13/4068: {Electrical coupling}
- H10W 72/00: Interconnections or connectors in packages
- H10W 90/00: Package configurations
- G06F 11/1423: {by reconfiguration of paths}
- G06F 2201/805: Real-time
- G06F 2201/82: Solving problems relating to consistency
- H10W 72/07254: {changes in dispositions}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

## Claims

### Claim 1

A memory module comprising:
a printed-circuit board with a module connector, the module connector having:
a first module data connection; and
a second module data connection;
a first memory component mounted to the printed-circuit board and having:
first memory;
a first data interface connected to the first module data connection, the first data interface to communicate between the first module data connection and the first memory; and
a second data interface to communicate with the first memory;
a second memory component mounted to the printed-circuit board and having:
second memory;
a third data interface connected to the second module data connection, the third data interface to communicate between the second module data connection and the second memory; and
a fourth data interface connected to the second data interface, the fourth data interface to communicate between the second data interface and the second memory; and
a mode register to store a mode value disabling the first data interface from communicating with the first module data connection.

### Claim 2 (depends on 1)

The memory module of claim 1, further comprising a buffer component that includes the mode register and is connected to the first memory component.

### Claim 3 (depends on 1)

The memory module of claim 1, the first memory to communicate with the second module data connection via the second, third, and fourth data interfaces responsive to the mode value.

### Claim 4 (depends on 1)

The memory module of claim 1, further comprising a buffer component to receive primary memory commands, derive secondary memory commands from the primary memory commands, and issue the secondary memory commands to the first memory component and the second memory component.

### Claim 5 (depends on 4)

The memory module of claim 4, wherein the buffer component includes the mode register.

### Claim 6 (depends on 1)

The memory module of claim 1, further comprising a connection ball connecting the fourth data interface to the second data interface.

### Claim 7 (depends on 1)

The memory module of claim 1, wherein the first memory component and the second memory component are combined in a stack.

### Claim 8 (depends on 1)

The memory module of claim 1, wherein the first memory and the second memory comprise dynamic, random-access memory cells.

### Claim 9

A method for communicating around a defective path to at least one of a first memory and a second memory on a memory module via a memory-module connector having a first module data connection and a second module data connection, the method comprising:
communicating first data with the first memory over the first module data connection via a first data interface;
communicating second data with the second memory over the second module data connection via a second data interface;
receiving a value indicating the first module data connection; and
responsive to the value:
disabling the first data interface;
communicating third data with the first memory over the second module data connection via the second data interface; and
communicating fourth data with the second memory over the second module data connection via the second data interface.

### Claim 10 (depends on 9)

The method of claim 9, further comprising communicating the third data with the first memory over a third data interface and a fourth data interface.

### Claim 11 (depends on 9)

The method of claim 9, further comprising storing the value in a register.

### Claim 12 (depends on 9)

The method of claim 9, further comprising conveying the third data and the fourth data to a memory controller via a second memory module.

### Claim 13 (depends on 12)

The method of claim 12, further comprising sending a second value to the second memory module, the second value configuring the second memory module to forward the third data and the fourth data to the memory controller.

### Claim 14 (depends on 9)

The method of claim 9, further comprising detecting a fault in the defective path and issuing the value responsive to the detecting.

### Claim 15

A memory module comprising:
a module connector having:
a first module data connection; and
a second module data connection;
a memory package having a stack of memory components, including:
a first memory component with a first package data interface connected to the first module data connection, the first package data interface to communicate between the first module data connection and a first memory in a first mode; and
a second memory component with a second package data interface connected to the second module data connection, the second package data interface to communicate between the second module data connection and a second memory in the first mode; and
a mode register connected to the memory package and storing a first mode value to select the first mode and a second mode value to select a second mode;
wherein the first memory component, in the second mode, communicates between the second module data connection and the first memory via the second package data interface.

### Claim 16 (depends on 15)

The memory module of claim 15, wherein the second memory component, in the second mode, communicates between the second module data connection and the second memory via the second package data interface.

### Claim 17 (depends on 15)

The memory module of claim 15, wherein the first package data interface includes a first data interface connected to the first module data connection and a second data interface connected to the second package data interface.

### Claim 18 (depends on 17)

The memory module of claim 17, wherein the second package data interface includes a third data interface connected to the second module data connection and a fourth data interface connected to the second data interface.

### Claim 19 (depends on 15)

The memory module of claim 15, further comprising a buffer component that includes a mode register and is connected to the memory package.

### Claim 20 (depends on 15)

The memory module of claim 15, wherein the first memory and the second memory comprise dynamic, random-access memory cells.