# US 12,216,539 B2 · Page retirement techniques for multi-page DRAM faults

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- Number: US 12,216,539 B2
- Document ID: US12216539B2
- Status: Granted
- Kind: B2
- Application number: 17/977,001
- Filed: 2022-10-31
- Published: 2024-05-02
- Granted: 2025-02-04
- Earliest claimed: 2022-10-31
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Sudhanva Gurumurthi; Vilas Sridharan; Majed Valad Beigi
- Web page: https://patentgrep.com/patent/US12216539B2

## CPC

- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).

## Claims

### Claim 1

A method comprising:
scrubbing a set of adjacent pages of a dynamic random access memory (DRAM) based on a miss at a translation lookaside buffer (TLB) of a page of the set; and
in response to detecting an uncorrectable error at a first page of the set, retiring a second page of the set.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
in response to the miss at the TLB, decoding a page offset of a virtual address of the miss at the TLB and returning an index of the set.

### Claim 3 (depends on 2)

The method of claim 2, wherein the decoding is by a hash function generating a set number to be inserted to a table of TLB miss sets.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
incrementing a counter in response to a miss to the set.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
recording the uncorrectable error detected at the first page at a fault map comprising a plurality of page addresses of pages having faults.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
scanning the fault map for page addresses adjacent to the first page in response to recording the uncorrectable error at the first page at the fault map.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
selecting a subset of page addresses for retirement based on the presence of an uncorrectable error at one or more pages of the subset, the subset including a page address of the second page.

### Claim 8 (depends on 4)

The method of claim 4, further comprising:
retiring the set of adjacent pages in response to the counter exceeding a threshold and detecting an uncorrectable error at the second page.

### Claim 9

A non-transitory computer-readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
scrub a set of adjacent pages of a dynamic random access memory (DRAM) based on a miss at a translation lookaside buffer (TLB) of a page of the set; and
retire a first page of the set, prior to accessing the first page in response to detecting an uncorrectable error at a second page of the set.

### Claim 10 (depends on 9)

The computer-readable medium of claim 9, wherein the set of executable instructions is to manipulate the processor to:
in response to the miss at the TLB, decode a page offset of a virtual address of the miss at the TLB and return an index of the set.

### Claim 11 (depends on 10)

The computer-readable medium of claim 10,
wherein the decoding is by a hash function generating a set number to be inserted to a table of TLB miss sets.

### Claim 12 (depends on 11)

The computer-readable medium of claim 11, wherein the set of executable instructions is to manipulate the processor to:
increment a counter in response to a miss to the set.

### Claim 13 (depends on 9)

The computer-readable medium of claim 9, wherein the set of executable instructions is to manipulate the processor to:
record the uncorrectable error detected at the second page at a fault map comprising a plurality of page addresses of pages having faults.

### Claim 14 (depends on 13)

The computer-readable medium of claim 13, wherein the set of executable instructions is to manipulate the processor to:
scan the fault map for page addresses adjacent to the second page in response to recording the uncorrectable error at the second page at the fault map.

### Claim 15 (depends on 14)

The computer-readable medium of claim 14, wherein the set of executable instructions is to manipulate the processor to:
select a subset of page addresses for retirement based on the presence of an uncorrectable error at one or more pages of the subset, the subset including a page address of the first page.

### Claim 16 (depends on 12)

The computer-readable medium of claim 12, wherein the set of executable instructions is to manipulate the processor to:
retire the set of adjacent pages in response to the counter exceeding a threshold and detecting an uncorrectable error at the first page.

### Claim 17

A device, comprising:
a dynamic random access memory (DRAM); and
control logic circuitry configured to:
scrub a set of adjacent pages of the DRAM based on a miss at a translation lookaside buffer (TLB) of a page of the set, and
in response to detecting an uncorrectable error at a first page of the set, retire a second page of the set.

### Claim 18 (depends on 17)

The device of claim 17, wherein the control logic circuitry is further to:
in response to the miss at the TLB, decode a page offset of a virtual address of the miss at the TLB and returning an index of the set.

### Claim 19 (depends on 18)

The device of claim 18, wherein the control logic circuitry is further to:
decode the page offset using a hash function to generate a set number to be inserted to a table of TLB miss sets.

### Claim 20 (depends on 19)

The device of claim 19, wherein the control logic circuitry is further to:
increment a counter in response to a miss to the set; and
retire the set of adjacent pages in response to the counter exceeding a threshold and detecting an uncorrectable error at the second page.