# US 12,216,529 B2 · Adaptive frequency control for high-speed memory devices

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- Number: US 12,216,529 B2
- Document ID: US12216529B2
- Status: Granted
- Kind: B2
- Application number: 17/933,443
- Filed: 2022-09-19
- Published: 2023-01-12
- Granted: 2025-02-04
- Earliest claimed: 2020-08-18
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jian Huang; Zhenming Zhou; Zhongguang Xu; Murong Lang
- Web page: https://patentgrep.com/patent/US12216529B2

## CPC

- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G06F 2201/81: Threshold
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G11C 2029/0403: {during or with feedback to manufacture}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

## Claims

### Claim 1

A method comprising:
operating both a memory controller and a memory die simultaneously at an initial operating frequency during a read operation;
detecting an occurrence of an error event during the read operation;
setting an error threshold criterion;
determining, with respect to the initial operating frequency, an adjusted value for a current operating frequency of at least one of the memory controller and the memory die;
determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion;
responsive the determining that the adjusted value of the current operating frequency satisfies the error threshold criterion, updating the operating frequency of the at least one of the memory controller or the memory die to the adjusted value of the current operating frequency; and
responsive the determining that the adjusted value of the current operating frequency does not satisfy the error threshold criterion, continuing to operate the memory controller and a memory die at the initial frequency.

### Claim 2 (depends on 1)

The method of claim 1, wherein the error event comprises an uncorrectable error correcting code (UECC) event.

### Claim 3 (depends on 1)

The method of claim 1, wherein determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion further comprises:
operating the memory die at the adjusted value for the current operating frequency;
repeating the read operation; and
detecting if the error event is repeated.

### Claim 4 (depends on 3)

The method of claim 3, wherein the error threshold criterion is associated with a predetermined reliability rating.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
responsive to determining that the error event is not repeated, assembling the memory die into a memory device having the predetermined reliability rating.

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
responsive to determining that the error event is repeated, screening out the memory die to be assembled into a memory device having a second reliability rating that is lower than the predetermined reliability rating.

### Claim 7 (depends on 3)

The method of claim 3, further comprising:
responsive to determining that the error event is repeated, further adjusting a value of the current operating frequency of the memory die until no error event is detected.

### Claim 8 (depends on 7)

The method of claim 7, wherein further adjusting the value of the current operating frequency is performed in predetermined steps.

### Claim 9 (depends on 1)

The method of claim 1, wherein determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion further comprises:
operating the memory controller at the adjusted value for the current operating frequency;
repeating the read operation; and
detecting if the error event is repeated.

### Claim 10 (depends on 1)

The method of claim 1, wherein the memory controller is in a test set up for screening the memory die for an appropriate level of reliability before the memory die is to be assembled into a memory device.

### Claim 11

A method comprising:
operating both a memory controller and a memory die simultaneously at an initial operating frequency during a read operation, wherein the memory controller is in a memory sub-system that controls the memory die after the memory die is assembled into a memory device;
detecting an occurrence of an error event during the read operation;
setting an error threshold criterion;
determining, with respect to the initial operating frequency, an adjusted value for a current operating frequency of at least one of the memory controller and the memory die;
determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion; and
responsive the determining that the adjusted value of the current operating frequency satisfies the error threshold criterion, updating the operating frequency of the at least one of the memory controller or the memory die to the adjusted value of the current operating frequency.

### Claim 12

A system comprising:
a plurality of memory dies; and
a processing device in a memory controller, operatively coupled to the plurality of memory dies, to perform operations for each of the plurality of memory dies, the operations comprising:
operating both a memory controller and a memory die simultaneously at an initial operating frequency during a read operation;
detecting an occurrence of an error event during the read operation;
setting an error threshold criterion;
determining, with respect to the initial operating frequency, an adjusted value for a current operating frequency of at least one of the memory controller and the memory die;
determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion;
responsive the determining that the adjusted value of the current operating frequency satisfies the error threshold criterion, updating the operating frequency of the at least one of the memory controller or the memory die to the adjusted value of the current operating frequency; and
responsive the determining that the adjusted value of the current operating frequency does not satisfy the error threshold criterion, continuing to operate the memory controller and a memory die at the initial frequency.

### Claim 13 (depends on 12)

The system of claim 12, wherein the error event comprises an uncorrectable error correcting code (UECC) event.

### Claim 14 (depends on 12)

The system of claim 12, wherein the operation of determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion further comprises:
operating the memory die at the adjusted value for the current operating frequency;
repeating the read operation; and
detecting if the error event is repeated.

### Claim 15 (depends on 14)

The system of claim 14, wherein the error threshold criterion is associated with a predetermined reliability rating.

### Claim 16 (depends on 15)

The system of claim 15, wherein the operations further comprises:
responsive to determining that the error event is not repeated, assembling the memory die into a memory device having the predetermined reliability rating.

### Claim 17 (depends on 15)

The system of claim 15, wherein the operations further comprises:
responsive to determining that the error event is repeated, screening out the memory die to be assembled into a memory device having a second reliability rating that is lower than the predetermined reliability rating.

### Claim 18 (depends on 12)

The system of claim 12, wherein the memory controller is in a test set up for screening the memory die for an appropriate level of reliability before the memory die is to be assembled into a memory device.

### Claim 19 (depends on 12)

The system of claim 12, wherein the memory controller is in a memory sub-system that controls the memory die after the memory die is assembled into a memory device.