# US 12,216,515 B2 · Current measurement for power converter circuits

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- Number: US 12,216,515 B2
- Document ID: US12216515B2
- Status: Granted
- Kind: B2
- Application number: 18/497,443
- Filed: 2023-10-30
- Published: 2024-04-18
- Granted: 2025-02-04
- Earliest claimed: 2021-03-24
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Shawn Searles; Fabio Gozzini; Sanjay Pant; Inder M. Sodhi
- Web page: https://patentgrep.com/patent/US12216515B2

## CPC

- G05F 1/46: wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence)
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G01R 15/146: {Measuring arrangements for current not covered by other subgroups of G01R15/14, e.g. using current dividers, shunts, or measuring a voltage drop (if no voltage isolation is involved G01R1/203 or G01R19/0092)}
- G01R 19/2506: {Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values (G01R19/003 takes precedence); Details concerning sampling, digitizing or waveform capturing (displaying waveforms G01R13/00; analog sampling G01R19/0053)}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.

## Claims

### Claim 1

An apparatus comprising:
a power converter configured to generate a regulated supply voltage, wherein the power converter includes a first phase circuit configured to generate a first demand current, wherein the first phase circuit includes:
a current sampling circuit configured to generate a stream of digital samples of the first demand current;
a first memory circuit configured to store a plurality of data words, wherein a given one of the plurality of data words comprises a plurality of digital samples; and
a trigger circuit configured to generate a trigger signal in response to detecting a trigger event in the stream of digital samples; and
a sample circuit coupled to the first phase circuit, wherein the sample circuit includes:
a control circuit configured to generate a timestamp value in response to generation of the trigger signal and further configured to generate an address indicative of a location in the first memory circuit storing a particular one of the plurality of digital samples corresponding to the trigger event.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the current sampling circuit includes:
a comparator configured to generate a demand current signal based on comparing a reference voltage to the regulated supply voltage; and
an analog-to-digital converter circuit configured to, in accordance with a clock signal, generate the stream of digital samples based on the demand current signal.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first phase circuit further includes:
a first-in first-out (FIFO) memory configured to receive and store digital samples of the stream of digital samples to form the plurality of digital samples, and, in response to determining all storage locations of the FIFO are full, transfer the plurality of digital samples to the first memory circuit as a given one of the plurality of data words; and
a pointer circuit configured to generate a pointer to a location in the FIFO memory in which a next one of the plurality of digital samples is to be stored.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the sample circuit further includes a second memory circuit configured to store timestamp values corresponding to trigger events indicated by assertions of the trigger signal.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the sample circuit further includes a register circuit configured to store trigger information received from a communication bus, wherein the trigger information is usable to initiate the trigger event.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the power converter includes a plurality of phase circuits including the first phase circuit, and wherein the power converter further includes a second control circuit configured to activate selected ones of the plurality of phase circuits based on the first demand current.

### Claim 7 (depends on 6)

The apparatus of claim 6, further comprising a communication bus coupled to the power converter, wherein the power converter is configured to generate a power control command in response to a determination that the first demand current exceeds a threshold for one or more of the plurality of phase circuits, and further configured to transmit the power control command onto the communication bus.

### Claim 8 (depends on 7)

The apparatus of claim 7, further comprising a load circuit coupled to receive the regulated supply voltage from the power converter, and further configured to receiver the power control command via the communication bus, wherein the load circuit is further configured to modify one or more operating parameters in response to receiving the power control command.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the one or more operating parameters include a frequency of a clock signal at which the load circuit operates.

### Claim 10

A method comprising:
generating, using a power converter, a regulated supply voltage;
generating, using a first phase circuit of the power converter, a first demand current;
generating, using a current sampling circuit of the first phase circuit, a stream of digital samples of the first demand current;
storing, in a first memory circuit, a plurality of data words, wherein a given one of the plurality of data words comprises a plurality of digital samples;
generating a trigger signal, using a trigger circuit, in response to detecting a trigger event in the stream of digital samples;
generating, using a sample circuit and in response to the generation of the trigger signal, a timestamp value; and
generating, using the sample circuit, an address indicative of a location in the first memory circuit storing a particular one of the plurality of digital samples corresponding to the trigger event.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
generating, using a comparator of the sampling circuit, a demand current signal based on a comparison of the regulated supply voltage to a reference voltage; and
generating, using the demand current signal and an analog-to-digital converter, the stream of digital samples.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
storing in a first-in first-out (FIFO) memory, digital samples of the stream of digital samples to form the plurality of digital samples,
transferring the plurality of digital samples to the first memory circuit as a given one of the plurality of data words in response to determining all storage locations of the FIFO are full, transfer; and
generating, using a pointer circuit, a pointer to a location in the FIFO memory in which a next one of the plurality of digital samples is to be stored.

### Claim 13 (depends on 11)

The method of claim 11, further comprising storing, in a second memory circuit, timestamp values corresponding to trigger events indicated by assertions of the trigger signal.

### Claim 14 (depends on 11)

The method of claim 11, further comprising storing, in a register circuit, trigger information received from a communication bus, wherein the trigger information is usable to initiate the trigger event.

### Claim 15 (depends on 10)

The method of claim 10, further comprising conveying, from the power converter to a load circuit coupled to receive the regulated supply voltage, a power command.

### Claim 16 (depends on 15)

The method of claim 15, further comprising conveying the power command via a communication bus.

### Claim 17 (depends on 16)

The method of claim 16, further comprising the load circuit adjusting one or more operating parameters in response to receiving the power command.

### Claim 18

A system comprising:
a load circuit;
a power converter configured to provide a regulated supply voltage to the load circuit, wherein the power converter includes a plurality of phase circuits, wherein ones of the plurality of phase circuits are configured to generate a demand current, and wherein a given one of the plurality of phase circuits includes:
a current sampling circuit configured to generate a stream of digital samples of the demand current;
a first memory circuit configured to store a plurality of data words, wherein a given one of the plurality of data words comprises a plurality of digital samples; and
a trigger circuit configured to generate a trigger signal in response to detecting a trigger event in the stream of digital samples; and
a sample circuit coupled to the plurality of phase circuits, wherein the sample circuit includes:
a first control circuit configured to generate a timestamp value in response to generation of the trigger signal by at least one of the plurality of phase circuits, and further configured to generate and address indicative of a location in the first memory circuit storing a particular one of the plurality of digital samples corresponding to the trigger event.

### Claim 19 (depends on 18)

The system of claim 18, wherein, in response to the trigger event, the power converter is configured to convey a power command to the load circuit, and wherein the load circuit is configured to, in response to receiving the power command, adjust one or more operating parameters.

### Claim 20 (depends on 18)

The system of claim 18, wherein the power converter includes a second control circuit configured to activate and deactivate ones of the plurality of phase circuits based on the demand current.