# US 12,216,488 B2 · Systems and methods for asynchronous finite machines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,488 B2 - Document ID: US12216488B2 - Status: Granted - Kind: B2 - Application number: 17/507,545 - Filed: 2021-10-21 - Published: 2023-04-27 - Granted: 2025-02-04 - Earliest claimed: 2021-10-21 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics S.r.l. - Inventors: Domenico Tripodi - Web page: https://patentgrep.com/patent/US12216488B2 ## CPC - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal. ## Claims ### Claim 1 A system comprising: a clockless trigger circuit comprising a first-state asynchronous event input to receive a first-state asynchronous event signal, and a second-state asynchronous event input to receive a second-state asynchronous event signal, wherein the clockless trigger circuit is configured to: assert a first trigger signal in response to the first-state asynchronous event signal being asserted while an asynchronous finite state machine is in a first state; and assert a second trigger signal in response to the second-state asynchronous event signal being asserted while the asynchronous finite state machine is in a second state; a clockless virtual clock-pulse circuit coupled to the clockless trigger circuit, and configured to: receive the first trigger signal and generate a first virtual-clock event in response to the first trigger signal being asserted; and receive the second trigger signal and generate a second virtual-clock event in response to the second trigger signal being asserted; and the asynchronous finite state machine, coupled to the clockless trigger circuit and the clockless virtual clock-pulse circuit, and configured to: generate a retimed first-state asynchronous event signal in response to receiving the first-state asynchronous event signal and the first virtual-clock event; transition from the first state to the second state in response to the retimed first-state asynchronous event signal and to the first virtual-clock event; and generate a retimed second-state asynchronous event signal in response to receiving the second-state asynchronous event signal and the second virtual-clock event; and transition from the second state to a third state in response to the retimed second-state asynchronous event signal and to the second virtual-clock event. ### Claim 2 (depends on 1) The system of claim 1, wherein the clockless trigger circuit comprises a multiplexer that comprises an output coupled with the clockless virtual clock-pulse circuit to deliver the first and second trigger signals, and a selection input that is coupled with an output of the asynchronous finite state machine, the clockless trigger circuit being configured to provide the first-state asynchronous event signal to the output of the clockless trigger circuit when the asynchronous finite state machine is in the first state and to provide the second-state asynchronous event signal to the output of the clockless trigger circuit when the asynchronous finite state machine is in the second state. ### Claim 3 (depends on 1) The system of claim 1, wherein the first virtual-clock event comprises a first pulse and a second pulse. ### Claim 4 (depends on 3) The system of claim 3, wherein the asynchronous finite state machine is configured to transition from the first state to the second state by transitioning from the first state to an intermediate state after receiving the first pulse and transition from the intermediate state to the second state after receiving the second pulse. ### Claim 5 (depends on 4) The system of claim 4, wherein the clockless trigger circuit is configured so that the first trigger signal is de-asserted when the asynchronous finite state machine is in the intermediate state. ### Claim 6 (depends on 4) The system of claim 4, wherein the asynchronous finite state machine is configured to transition from the first state to the intermediate state on receiving a second-in-time active edge of the first pulse and configured to transition from the intermediate state to the second state on receiving a second-in-time active edge of the second pulse. ### Claim 7 (depends on 3) The system of claim 3 wherein the clockless virtual clock-pulse circuit comprises: a monostable circuit to generate the first pulse; and a pulse doubling circuit to generate the second pulse. ### Claim 8 (depends on 1) The system of claim 1, further comprising a de-glitch circuit comprising: an input coupled with an output of the clockless trigger circuit; and an output coupled with the clockless virtual clock-pulse circuit. ### Claim 9 (depends on 1) The system of claim 1, wherein the second virtual-clock event comprises a first pulse of the second virtual-clock event and a second pulse of the second virtual-clock event. ### Claim 10 A method comprising: triggering, by a clockless trigger circuit, a first trigger signal in response to a first-state asynchronous event signal being asserted; providing, by a clockless virtual clock-pulse circuit, a first virtual-clock event to an asynchronous finite state machine; generating, by the asynchronous finite state machine, a retimed first-state asynchronous event signal in response to receiving a first pulse of the first virtual-clock event and a first-state event signal; transitioning the asynchronous finite state machine from a first state to a second state in response to the retimed first-state asynchronous event signal and to the first virtual-clock event; triggering, by the clockless trigger circuit, a second trigger signal in response to receiving a second-state asynchronous event signal; providing, by the clockless virtual clock-pulse circuit, a second virtual-clock event to the asynchronous finite state machine; generating, by the asynchronous finite state machine, a retimed second-state asynchronous event signal in response to receiving a first pulse of the second virtual-clock event and the second-state asynchronous event signal; and transitioning the asynchronous finite state machine from the second state to a third state in response to the retimed second-state asynchronous event signal and to the second virtual-clock event. ### Claim 11 (depends on 10) The method of claim 10, wherein transitioning the asynchronous finite state machine from the first state to the second state comprises: transitioning the asynchronous finite state machine from the first state to an intermediate state; and transitioning the asynchronous finite state machine from the intermediate state to the second state. ### Claim 12 (depends on 11) The method of claim 11, wherein providing the first virtual-clock event to the asynchronous finite state machine comprises: providing the first pulse of the first virtual-clock event to the asynchronous finite state machine; and providing a second pulse of the first virtual-clock event to the asynchronous finite state machine. ### Claim 13 (depends on 12) The method of claim 12, further comprising: transitioning the asynchronous finite state machine from the first state to the intermediate state in response to a second-in-time active edge of the first pulse of the first virtual-clock event; and transitioning the asynchronous finite state machine from the intermediate state to the second state in response to a second-in-time active edge of the second pulse of the first virtual-clock event. ### Claim 14 (depends on 10) The method of claim 10, wherein transitioning the asynchronous finite state machine from the second state to the third state comprises: transitioning the asynchronous finite state machine from the second state to an intermediate state; and transitioning the asynchronous finite state machine from the intermediate state to the third state. ### Claim 15 (depends on 14) The method of claim 14, wherein providing the second virtual-clock event to the asynchronous finite state machine comprises providing first and second pulses of the second virtual-clock event to the asynchronous finite state machine, and the method further comprises: transitioning the asynchronous finite state machine from the second state to the intermediate state in response to a second-in-time active edge of the first pulse of the second virtual-clock event; and transitioning the asynchronous finite state machine from the intermediate state to the third state in response to a second-in-time active edge of the second pulse of the second virtual-clock event. ### Claim 16 A system comprising: a clockless trigger circuit comprising a first-state asynchronous event input to receive a first-state asynchronous event signal, and a second-state asynchronous event input to receive a second-state asynchronous event signal, wherein the clockless trigger circuit is configured to: assert a first trigger signal in response to the first-state asynchronous event signal being asserted while an asynchronous finite state machine is in a first state; and assert a second trigger signal when the second-state asynchronous event signal is asserted while the asynchronous finite state machine is in a second state; a clockless virtual clock-pulse circuit coupled to the clockless trigger circuit, and configured to receive the first and second trigger signals and generate first and second virtual-clock events in response to the first and second trigger signals, respectively, being asserted; and the asynchronous finite state machine, coupled to the clockless trigger circuit and the clockless virtual clock-pulse circuit, and configured to: generate a retimed first-state asynchronous event signal in response to receiving a first pulse of the first virtual-clock event while in the first state; transition from the first state to a first intermediate state in response to the retimed first-state asynchronous event signal; transition from the first intermediate state to the second state in response to receiving a second pulse of the first virtual-clock event while in the first intermediate state; generate a retimed second-state asynchronous event signal in response to receiving a first pulse of the second virtual-clock event while in the second state; transition from the second state to a second intermediate state in response to the retimed second-state asynchronous event signal; and transition from the second intermediate state to a third state in response to receiving a second pulse of the second virtual-clock event while in the second intermediate state. ### Claim 17 (depends on 16) The system of claim 16, wherein the clockless trigger circuit is configured to: de-assert the first trigger signal when the asynchronous finite state machine is in the first intermediate state; and de-assert the second trigger signal when the asynchronous finite state machine is in the second intermediate state. ### Claim 18 (depends on 16) The system of claim 16, wherein the asynchronous finite state machine is configured to: transition from the first state to the first intermediate state on receiving a second-in-time active edge of the first pulse of the first virtual-clock event; and transition from the first intermediate state to the second state on receiving a second-in-time active edge of the second pulse of the first virtual-clock event. ### Claim 19 (depends on 16) The system of claim 16, wherein the asynchronous finite state machine is configured to: transition from the second state to the second intermediate state on receiving a second-in-time active edge of the first pulse of the second virtual-clock event; and transition from the second intermediate state to the third state on receiving the second-in-time active edge of the second pulse of the second virtual-clock event. ### Claim 20 (depends on 16) The system of claim 16, wherein the clockless virtual clock-pulse circuit comprises: a monostable circuit configured to generate the first pulses of the first and second virtual-clock events; and a pulse-doubling circuit to generate the second pulses of the first and second virtual-clock events. ### Claim 21 (depends on 16) The system of claim 16, further comprising a de-glitch circuit comprising: an input coupled with an output of the clockless trigger circuit; and an output coupled with the clockless virtual clock-pulse circuit.