Processor circuit for generating ultrafast clock multiplier

A non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor, cause the at least one processor to:

• instruct a beam splitter of a photonic circuit to receive a photonic seed clock signal and split the photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal;
• instruct a phase shifter of the photonic circuit to receive a photonic signal and shift a phase of the photonic signal to generate a phase-shifted version of the photonic signal;
• instruct a first photonic combiner of the photonic circuit coupled to the beam splitter and the phase shifter to combine the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal;
• and
• instruct a second photonic combiner of the photonic circuit coupled to the beam splitter and the first photonic combiner to combine a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.

A method comprising:

• splitting, by a beam splitter of a photonic circuit, a photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal;
• shifting, by a phase shifter of the photonic circuit, a phase of a photonic signal to generate a phase-shifted version of the photonic signal;
• combining, by a first photonic combiner of the photonic circuit coupled to the beam splitter and the phase shifter, the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal;
• and
• combining, by a second photonic combiner of the photonic circuit coupled to the beam splitter and the first photonic combiner, a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.