# US 12,216,344 B2 · Optical modulator and method of fabricating an optical modulator

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- Number: US 12,216,344 B2
- Document ID: US12216344B2
- Status: Granted
- Kind: B2
- Application number: 17/753,193
- Filed: 2020-08-25
- Published: 2022-09-01
- Granted: 2025-02-04
- Earliest claimed: 2019-08-26
- Assignees: Rockley Photonics Limited
- Applicants: Rockley Photonics Limited
- Inventors: Adam Scofield
- Web page: https://patentgrep.com/patent/US12216344B2

## CPC

- G02F 1/025: in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence)
- G02B 6/12: of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00)
- G02B 6/12004: {Combinations of two or more optical elements}
- G02B 2006/12061: {Silicon}
- G02B 2006/12142: {Modulator}
- G02B 2006/12173: {Masking}
- G02B 2006/12176: {Etching}
- G02B 2006/12178: {Epitaxial growth}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS

## Abstract

A MOS capacitor-type optical modulator comprising a silicon-on-insulator (SOI) substrate, a first doped region in a silicon device layer of the SOI substrate, and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region. The first doped region, second doped region and insulator layer are formed from different materials.

## Claims

### Claim 1

A MOS capacitor-type optical modulator comprising:
a silicon-on-insulator (SOI) substrate;
a first doped region in a silicon device layer of the SOI substrate; and
a second doped crystalline region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region, wherein the first doped region, second doped crystalline region and insulator layer are formed from different materials,
wherein the insulator layer extends at an oblique angle relative to the substrate, so as to laterally separate the second doped crystalline region from the first doped region.

### Claim 2 (depends on 1)

The MOS capacitor-type optical modulator of claim 1, wherein the second doped crystalline region is formed in a type III-V semiconductor region.

### Claim 3 (depends on 1)

The MOS capacitor-type optical modulator of claim 1, wherein the insulator layer comprises silicon nitride.

### Claim 4 (depends on 1)

The MOS capacitor-type optical modulator of claim 1, wherein the silicon device layer of the SOI substrate has a (100) crystalline orientation.

### Claim 5 (depends on 1)

The MOS capacitor-type optical modulator of claim 1, wherein a first portion of the insulator layer extends horizontally on top of the first doped region, and a second portion of the insulator layer extends horizontally beneath the second doped crystalline region.

### Claim 6 (depends on 1)

A method of fabricating the MOS capacitor-type optical modulator of claim 1, wherein the method comprises the steps of:
providing the first doped region in the silicon device layer; and
epitaxially growing a semiconductor region from the silicon device layer of the SOI substrate, wherein the semiconductor region comprises the second doped crystalline region, and the first doped region, second doped crystalline region and insulator layer are each formed from different materials.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the semiconductor region is epitaxially grown from a region of the silicon device layer laterally offset from the lateral MOS capacitor region.

### Claim 8 (depends on 6)

The method according to claim 6, wherein the semiconductor region is a type III-V semiconductor region.

### Claim 9 (depends on 6)

The method according to claim 6, wherein the silicon device layer of the SOI substrate has a (100) crystalline structure.

### Claim 10 (depends on 6)

The method according to claim 6, wherein the method further comprises the step of:
etching a portion of the semiconductor region to form a waveguide structure, the waveguide structure comprising the lateral MOS capacitor region.

### Claim 11 (depends on 10)

The method according to claim 10, further comprising the steps of:
depositing an isolation layer on the waveguide structure;
applying a first electrical contact through the isolation layer to the first doped region; and
applying a second electrical contact through the isolation layer to the second doped crystalline region.

### Claim 12 (depends on 6)

The method according to claim 6, wherein the method further comprises the steps of:
creating a cavity underneath an upper mask layer; and
epitaxially growing the semiconductor region from the silicon device layer of the SOI substrate in the cavity.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the upper mask layer comprises silicon nitride.

### Claim 14 (depends on 12)

The method according to claim 12, wherein the step of creating the cavity comprises:
providing a sacrificial layer;
depositing the upper mask layer on top of the sacrificial layer; and
selectively etching the sacrificial layer to create the cavity.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the method further comprises the steps of:
etching a trench in the silicon device layer of the SOI substrate;
depositing a lower mask layer on top of the silicon device layer and in the trench;
etching an opening in the lower mask layer to the silicon device layer at a region of the silicon device layer laterally offset from the lateral MOS capacitor region; and
depositing the sacrificial layer on the lower mask layer and in the opening in the lower mask layer.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising the step of etching a portion of the sacrificial layer to the lower mask layer before depositing the upper mask layer.

### Claim 17 (depends on 14)

The method according to claim 14, wherein the method further comprises the step of planarizing the sacrificial layer by Chemical Mechanical Planarization, CMP.

### Claim 18 (depends on 14)

The method according to claim 14, wherein the sacrificial layer comprises aluminium oxide or amorphous silicon.

### Claim 19 (depends on 1)

A method of fabricating the MOS capacitor-type optical modulator of claim 1, the method comprising the steps of:
creating a cavity underneath an upper mask layer; and
epitaxially growing a semiconductor region, comprising the second doped crystalline region, from the silicon device layer in the cavity.