# US 12,216,226 B2 · Radar system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,226 B2 - Document ID: US12216226B2 - Status: Granted - Kind: B2 - Application number: 17/661,944 - Filed: 2022-05-04 - Published: 2022-11-17 - Granted: 2025-02-04 - Earliest claimed: 2021-05-12 - Assignees: NXP B.V. - Applicants: NXP B.V. - Inventors: Ulrich Moehlmann; Cristian Pavao Moreira; Andreas Johannes Köllmann - Web page: https://patentgrep.com/patent/US12216226B2 ## CPC - G01S 7/40: Means for monitoring or calibrating - H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) - G01S 7/032: {Constructional details for solid-state radar subsystems} - G01S 7/35: Details of non-pulse systems - G01S 7/4017: {of HF systems} - G01S 7/4021: {of receivers} - G01S 13/87: Combinations of radar systems, e.g. primary radar and secondary radar - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/099: concerning mainly the controlled oscillator of the loop - G01S 2013/0254: {Active array antenna} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307). ## Claims ### Claim 1 A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising: a phase comparator connected to receive the first clock signal and a feedback signal; a loop filter connected to receive an output signal from the phase comparator; a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal; wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and wherein the divide by n clock divider comprises five flip-flops, FFs, arranged to receive the second clock signal from the second oscillator, three OR gates and one AND gate arranged to receive outputs from the FFs. ### Claim 2 (depends on 1) The radar system of claim 1, wherein the output of the multiplexer in each of the plurality of radar transceiver modules is connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver. ### Claim 3 (depends on 1) The radar system of claim 1, wherein n is an odd integer of 3 or more. ### Claim 4 (depends on 3) The radar system of claim 3, wherein n=3, 5 or 7. ### Claim 5 (depends on 1) The radar system of claim 1 wherein the divide by n clock divider comprises three inverters connected to a respective OR gate output, 3 of the phase shifted clock signals being output by the OR gates and another 3 of the phase shifted clock signals being output by the inverters. ### Claim 6 (depends on 1) The radar system of claim 1, wherein the divide by n clock divider comprises eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals. ### Claim 7 (depends on 1) The radar system of claim 1, wherein the divide by n clock divider comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals. ### Claim 8 (depends on 1) The radar system of claim 1, wherein the first frequency is in a range of between around 1 and 100 MHz. ### Claim 9 (depends on 1) The radar system of claim 1, wherein the third frequency is in a range between around 1 and 10 GHz. ### Claim 10 (depends on 1) The radar system of claim 1, comprising a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system. ### Claim 11 (depends on 1) The radar system of claim 1, wherein the feedback device in each of the plurality of radar transceiver modules is a divide-by-m clock divider and/or a time-to-digital converter. ### Claim 12 (depends on 1) A method of calibrating a radar system according to claim 1, the method comprising: operating each of the plurality of radar transceiver modules to detect a target; determine a phase select signal for the divide by n clock divider of the PLL clock signal generator in each module to minimize a difference in phase between the third clock signal in each follower module and in the leader module; and storing the determined phase select signal for each of the plurality of radar transceiver modules in a non-volatile memory. ### Claim 13 (depends on 1) A method of operating a radar system according to claim 1, the method comprising: retrieving a phase select signal for each of the plurality of radar transceiver modules from a non-volatile memory; and operating each of the plurality of radar transceiver modules while providing the retrieved phase select signal to the divide by n clock divider of the PLL clock signal generator in each module. ### Claim 14 (depends on 13) The method of claim 13, wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency. ### Claim 15 (depends on 13) The method of claim 13, wherein the output of the multiplexer in each of the plurality of radar transceiver modules is connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver. ### Claim 16 (depends on 13) The method of claim 13, wherein the radar system comprises a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system. ### Claim 17 (depends on 13) The method of claim 13, wherein the feedback device in each of the plurality of radar transceiver modules is a divide-by-m clock divider and/or a time-to-digital converter. ### Claim 18 (depends on 13) The method of claim 13, wherein the first frequency is in a range of between around 1 and 100 MHz. ### Claim 19 A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising: a phase comparator connected to receive the first clock signal and a feedback signal; a loop filter connected to receive an output signal from the phase comparator; a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal; wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and wherein the divide by n clock divider comprises eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals. ### Claim 20 A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising: a phase comparator connected to receive the first clock signal and a feedback signal; a loop filter connected to receive an output signal from the phase comparator; a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal; wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and wherein the divide by n clock divider comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals.