# US 12,216,164 B2 · Output voltage glitch reduction in test systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,164 B2 - Document ID: US12216164B2 - Status: Granted - Kind: B2 - Application number: 17/904,935 - Filed: 2021-02-24 - Published: 2023-06-08 - Granted: 2025-02-04 - Earliest claimed: 2020-02-24 - Assignees: Analog Devices, Inc. - Applicants: Analog Devices, Inc. - Inventors: Michael E. Harrell; Anthony Eric Turvey; Stefano I D'Aquino; Jennifer W. Pierdomenico - Web page: https://patentgrep.com/patent/US12216164B2 ## CPC - G01R 31/31924: {Voltage or current aspects, e.g. driver, receiver} - G01R 31/2834: {Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736)} - H03F 1/523: {for amplifiers using field-effect devices (H03F1/526 takes precedence)} - H03F 3/04: with semiconductor devices only - H03F 3/16: with field-effect devices - H03F 3/301: {CMOS common drain output SEPP amplifiers (H03F3/3008 takes precedence)} - H03F 2200/441: Protection of an amplifier being implemented by clamping means - H03F 2200/444: Diode used as protection means in an amplifier, e.g. as a limiter or as a switch - H03F 2200/453: Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03F: AMPLIFIERS ## Abstract A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value. ## Claims ### Claim 1 A clamp circuit comprising: an output to provide an output current at a clamped current level; an output transistor and a replica transistor coupled as a current mirror pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value; a voltage source circuit coupled to the replica transistor, and changing the register value changes voltage of the voltage source circuit to change the clamped output current value and, wherein the voltage source circuit includes a first diode connected transistor and a second diode connected transistor, wherein a current density of the first diode connected transistor is different from a current density of the second diode connected transistor, and the voltage of the voltage source is a difference in gate-to-source voltage between the first diode connected transistor and the second diode connected transistor. ### Claim 2 (depends on 1) The clamp circuit of claim 1, including: a second current source; wherein the replica transistor is a field effect transistor (FET) and the second current source is coupled to a source or drain region of the replica transistor; and wherein changing the register value changes current of the second current source to change a gate-to-source voltage of the replica transistor to set the clamped output current value. ### Claim 3 (depends on 1) The clamp circuit of claim 1, wherein the replica transistor is a field effect transistor (FET), and the voltage source circuit is coupled to a source or drain region of the FET. ### Claim 4 (depends on 1) The clamp circuit of claim 1, wherein the replica transistor is a field effect transistor (FET), the first diode connected transistor is connected to the output transistor, and the second diode connected transistor is connected in series to a source or drain region of the replica transistor. ### Claim 5 (depends on 1) The clamp circuit of claim 1, a third transistor coupled to the first current source; wherein the replica transistor is coupled to the third transistor to mirror current of the third transistor; and wherein changing the register value changes current of the first current source to set the clamped output current value. ### Claim 6 An automated testing system, the system comprising: a switch circuit coupled to an input/output (I/O) connection of the system; a force amplifier (FA) coupled to the switch circuit; a first adjustable current clamp circuit coupled to an output transistor of the FA, the first adjustable current clamp circuit including: a replica transistor coupled as a current mirror pair to the output transistor of the FA, wherein the replica transistor is a field effect transistor (FET) and is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein an output current of the FA is set to a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; a second current source coupled to a source or drain region of the replica transistor, and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value; and a control circuit configured to activate the switch circuit and change the register value to change current of the second current source and a gate-to-source voltage of the replica transistor to change the clamped output current value of output current of the FA. ### Claim 7 (depends on 6) The system of claim 6, wherein the first adjustable current source includes: a voltage source circuit coupled to the replica transistor, and the control circuit is configured to change the register value to change voltage of the voltage source circuit to change the clamped output current value of output current of the FA. ### Claim 8 (depends on 7) The system of claim 7, wherein the voltage source circuit of the first adjustable current source includes a first diode connected transistor and a second diode connected transistor, wherein a current density of the first diode connected transistor is different from a current density of the second diode connected transistor, and the voltage of the voltage source circuit is a difference in gate-to-source voltage between the first diode connected transistor and the second diode connected transistor. ### Claim 9 (depends on 8) The system of claim 8, wherein the first diode connected transistor is connected to the output transistor of the FA, and the second diode connected transistor is connected in series to a source or drain region of the replica transistor. ### Claim 10 (depends on 6) The system of claim 6, wherein the first adjustable current clamp circuit includes: a third transistor coupled to the first current source; wherein the replica transistor is coupled to the third transistor to mirror current of the third transistor; and wherein the control circuit is configured to change the register value to change current of the first current source to set the clamped output current value of output current of the FA. ### Claim 11 (depends on 6) The system of claim 6, including: a low side switch circuit coupled to the I/O connection; a low side force amplifier (LFA) coupled to the low side switch; a second adjustable current clamp circuit coupled to an output transistor of the FA; and wherein the control circuit is configured to change the current of one or both of the first adjustable clamp circuit and the second adjustable clamp circuit to change the control of current at the I/O connection from one of the FA or LFA to the other of the FA or LEA. ### Claim 12 (depends on 11) The system of claim 11, wherein the first adjustable clamp circuit clamps the output current of the FA to a higher range of clamp current levels than the second adjustable clamp circuit clamps the output current of the LFA. ### Claim 13 An amplifier comprising: an output circuit stage having an output transistor; and an adjustable current clamp circuit coupled to the output transistor, wherein the adjustable current clamp circuit includes: a replica transistor coupled as a current mirror pair to the output transistor of the output circuit stage, wherein the replica transistor is a field effect transistor (FET) and is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein an output current of the amplifier is set to a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; a second current source coupled to a source or drain region of the replica transistor, and a register circuit, wherein a register value stored in the register circuit sets current of the second current source to set a gate-to-source voltage of the replica transistor to set the clamped output current value. ### Claim 14 (depends on 13) The amplifier of claim 13, wherein the adjustable current clamp circuit includes: a voltage source circuit; wherein the voltage source circuit is coupled to a source or drain region of the replica transistor, and the register value stored in the register circuit sets voltage of voltage source circuit to set the clamped output current value. ### Claim 15 (depends on 14) The amplifier of claim 14, wherein the voltage source circuit includes a first diode connected transistor and a second diode connected transistor, wherein a current density of the first diode connected transistor is different from a current density of the second diode connected transistor, and the voltage of the voltage source is a difference in gate-to-source voltage between the first diode connected transistor and the second diode connected transistor. ### Claim 16 (depends on 15) The amplifier of claim 15, wherein the first diode connected transistor is connected to the output transistor, and the second diode connected transistor is connected in series to a source or drain region of the replica transistor.