# US 12,216,163 B2 · Systems and methods of testing devices using CXL for increased parallelism

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- Number: US 12,216,163 B2
- Document ID: US12216163B2
- Status: Granted
- Kind: B2
- Application number: 18/105,792
- Filed: 2023-02-03
- Published: 2024-03-21
- Granted: 2025-02-04
- Earliest claimed: 2022-09-15
- Assignees: Advantest Corporation
- Applicants: Advantest Corporation
- Inventors: Edmundo De La Puente
- Web page: https://patentgrep.com/patent/US12216163B2

## CPC

- G01R 31/31907: {Modular tester, e.g. controlling and coordinating instruments in a bus based architecture}
- G01R 31/31926: {Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing}
- G06F 11/221: {to test buses, lines or interfaces, e.g. stuck-at or open line faults}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.

## Claims

### Claim 1

A circuit for bifurcating bus lanes of a processor, the circuit comprising:
a plurality of input ports for coupling to four 16-bit buses from said processor wherein each of said four 16-bit buses comprises a lower set of bits and a higher set of bits;
a plurality of output ports for providing four 8-bit buses;
multiplexing circuitry coupled to said plurality of input ports and coupled to said plurality of output ports, said multiplexing circuitry responsive to a common select line for selectively implementing one of two configurations comprising:
a first configuration which couples said plurality of output ports to only lower halves sets of bits of said four 16-bit buses from said processor; and
a second configuration which couples said plurality of output ports to lower and higher halves sets of bits of at least two of said four 16-bit buses from said processor, wherein two of the four 8-bit buses are operable to be coupled to a first device under test (DUT) for testing said first DUT, and wherein the other two of the four 8-bit buses are operable to be coupled to a second DUT for testing said second DUT in the second configuration.

### Claim 2 (depends on 1)

The circuit as described in claim 1, wherein said multiplexing circuitry comprises a plurality of high-speed multiplexers, each high-speed multiplexer coupled to said common select line.

### Claim 3 (depends on 2)

The circuit as described in claim 2, wherein said plurality of high-speed multiplexers comprise two multiplexers.

### Claim 4 (depends on 1)

The circuit as described in claim 1, wherein said first and said second configurations are operable to be dynamically configured based on a value of said common select line.

### Claim 5

A tester circuit for testing devices under test (DUTs), said tester circuit comprising:
a processor having four 16-bit buses;
a plurality of input ports coupled said four 16-bit buses of said processor wherein each of said four 16-bit buses comprises a lower set of bits and a higher set of bits;
a plurality of output ports for providing four 8-bit buses; and
high-speed multiplexing circuitry coupled to said plurality of input ports and coupled to said plurality of output ports, said high-speed multiplexing circuitry responsive to a common select line for selectively implementing one of two configurations comprising:
a first configuration which couples said plurality of output ports to only lower halves of said four 16-bit buses from said processor, wherein each of the four 8-bit buses are operable to be coupled to four respective devices under test (DUTs) for testing said DUTs in the first configuration; and
a second configuration which couples said plurality of output ports to lower and higher halves of at least two of said four 16-bit buses from said processor.

### Claim 6 (depends on 5)

The tester circuit as described in claim 5, wherein said high-speed multiplexing circuitry comprises a plurality of high-speed multiplexers each high-speed multiplexer coupled to said common select line.

### Claim 7 (depends on 5)

The circuit as described in claim 5, wherein said first and said second configurations are operable to be dynamically configured.

### Claim 8

A method of bifurcating buses of a processor for testing, said method comprising:
a processor generating signals over at least four 16-bit buses;
in a first mode of operation, multiplexer circuitry coupled to said at least four 16-bit buses of said processor, and disposed external to said processor, generating signals over four 8-bit output buses;
in said first mode of operation, using said processor to simultaneously test four devices under test (DUTs) with said four 8-bit output buses;
in a second mode of operation, said multiplexer circuitry generating signals over two 16-bit output buses;
in said second mode of operation, using said processor to simultaneously test two DUTs with said two 16-bit output buses; and
switching between said first mode and said second mode of operation by switching a value of a select line coupled to said multiplexing circuitry.

### Claim 9 (depends on 8)

A method as described in claim 8, wherein said multiplexer circuitry comprises high-speed multiplexers commonly coupled to said select line.

### Claim 10 (depends on 9)

The method as described in claim 9, wherein said high-speed multiplexers comprise two multiplexers.