# US 12,216,161 B2 · Scan chain analysis using predefined capture signature > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,216,161 B2 - Document ID: US12216161B2 - Status: Granted - Kind: B2 - Application number: 18/323,946 - Filed: 2023-05-25 - Published: 2024-11-28 - Granted: 2025-02-04 - Earliest claimed: 2023-05-25 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Bo Yang; Antonietta Oliva; Michael R. Seningen; Vasu P. Ganti; Vijay M. Bettada - Web page: https://patentgrep.com/patent/US12216161B2 ## CPC - G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals} - G01R 31/318566: {Comparators; Diagnosing the device under test} - G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)} - G01R 31/318558: {Addressing or selecting of subparts of the device under test} - G01R 31/318563: {Multiple simultaneous testing of subparts} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface. ## Claims ### Claim 1 An apparatus comprising: a plurality of circuit blocks; a plurality of scan-enabled flip-flop circuits, coupled in a sequential manner across the plurality of circuit blocks, configured to shift a scan chain test signal from a test input interface to a test output interface; and a plurality of scan signature circuits, coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and configured to: in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits; and wherein the plurality of scan-enabled flip-flop circuits is further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein to concurrently load the known scan-chain pattern, a given one of the plurality of scan signature circuits is configured to shift a corresponding portion of the known scan-chain pattern into a scan input node of a respective one of the subset of scan-enabled flip-flop circuits. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the plurality of scan signature circuits is further configured to select, based on a value of the particular test signal, one of a plurality of known scan-chain patterns to concurrently load into the subset of the scan-enabled flip-flop circuits. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein a first pattern of the plurality of known scan-chain patterns is a repetitive pattern of a particular sequence of high and low logic states. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein a first pattern of the plurality of known scan-chain patterns is an inverse of a second pattern of the plurality of known scan-chain patterns. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein a given scan-enabled flip-flop circuit is configured to receive a data input signal that is derived based on a plurality of logic paths that include respective scan-enabled flip-flop circuits, and wherein the given scan-enabled flip-flop circuit is excluded from coupling to a respective scan signature circuit. ### Claim 7 (depends on 1) The apparatus of claim 1, further including a test circuit configured to: identify a failing one of the plurality of scan-enabled flip-flop circuits; and enable an alternate scan chain path that avoids the failing scan-enabled flip-flop circuit in the scan chain. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the plurality of scan signature circuits is included within the respective ones of the subset of the plurality of scan-enabled flip-flop circuits. ### Claim 9 A method, comprising: shifting, by a scan chain that includes a plurality of scan-enabled flip-flop circuits, a scan-chain pattern from an input port of a test interface of an integrated circuit to an output port of the test interface, wherein at least one of the plurality of scan-enabled flip-flop circuits fails to shift the scan-chain pattern; after the scan-chain pattern fails to be shifted to the output port, concurrently loading, by a plurality of scan signature circuits that are coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits; and shifting, by a functioning portion of the scan chain, at least a portion of the known scan-chain pattern to the output port. ### Claim 10 (depends on 9) The method of claim 9, wherein the functioning portion of the scan chain includes a sequence of the plurality of scan-enabled flip-flop circuits arranged between a failing one of the plurality of scan-enabled flip-flop circuits and the output port. ### Claim 11 (depends on 9) The method of claim 9, further comprising: after shifting the at least the portion of the known scan-chain pattern to the output port, concurrently loading, by the plurality of scan signature circuits, an inverse of the known scan-chain pattern to the subset of the scan-enabled flip-flop circuits; and shifting, by the functioning portion of the scan chain, at least a portion of the inverse of the known scan-chain pattern to the output port. ### Claim 12 (depends on 9) The method of claim 9, wherein concurrently loading the known scan-chain pattern includes: asserting, by a first scan signature circuit, a set node of a respective one of the subset of scan-enabled flip-flop circuits; and asserting, by a second scan signature circuit while the first scan signature circuit asserts the set node, a reset node of a different one of the subset of scan-enabled flip-flop circuits. ### Claim 13 (depends on 9) The method of claim 9, further comprising configured to: identifying, by a test circuit, a failing one of the plurality of scan-enabled flip-flop circuits; and enabling, by the test circuit, an alternate scan chain path that avoids the failing scan-enabled flip-flop circuit in the scan chain. ### Claim 14 (depends on 13) The method of claim 13, wherein enabling the alternate scan chain path includes enabling a bypass switch circuit to route an input node of the failing scan-enabled flip-flop circuit to an output node of the failing scan-enabled flip-flop circuit. ### Claim 15 A computer-readable, non-transitory storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor manufacturing system that is configured to use the design information to produce the hardware integrated circuit according to the design information, and wherein the design information specifies that the hardware integrated circuit comprises: a plurality of circuit blocks; a plurality of scan-enabled flip-flop circuits, forming one or more scan chains across the plurality of circuit blocks, configured to shift a scan chain test signal from a test input interface to a test output interface; and a plurality of scan signature circuits, included in respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and configured to concurrently load, in response to a particular signal, a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits; and wherein the plurality of scan-enabled flip-flop circuits is further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface. ### Claim 16 (depends on 15) The computer-readable, non-transitory storage medium of claim 15, wherein the plurality of scan signature circuits is further configured to concurrently load a selected one of a plurality of known scan-chain patterns to the subset of the scan-enabled flip-flop circuits based on a value of the particular signal. ### Claim 17 (depends on 15) The computer-readable, non-transitory storage medium of claim 15, wherein the known scan-chain pattern is a repetitive pattern of a particular sequence of high and low logic states. ### Claim 18 (depends on 15) The computer-readable, non-transitory storage medium of claim 15, wherein the plurality of scan-enabled flip-flop circuits form a plurality of scan chains and includes a given scan-enabled flip-flop circuit that is configured to receive a data input signal that is derived from a threshold number of the plurality of scan chains, and wherein the given scan-enabled flip-flop circuit is excluded from the subset of the plurality of scan-enabled flip-flop circuits. ### Claim 19 (depends on 15) The computer-readable, non-transitory storage medium of claim 15, wherein the hardware integrated circuit further comprises: a test circuit configured to: identify a failing one of the plurality of scan-enabled flip-flop circuits; and enable an alternate scan chain path that avoids the failing scan-enabled flip-flop circuit in the scan chain. ### Claim 20 (depends on 19) The computer-readable, non-transitory storage medium of claim 19, wherein to enable the alternate scan chain path, the test circuit is further configured to: activate a first set of bypass switch circuits to route an input node of the failing scan-enabled flip-flop circuit to an input node of a spare scan-enabled flip-flop circuit; and activate a second set of bypass switch circuits to route an output node of the spare scan-enabled flip-flop circuit to an output node of the failing scan-enabled flip-flop circuit.