# US 12,216,160 B2 · Clock shaper circuit for transition fault testing

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,216,160 B2
- Document ID: US12216160B2
- Status: Granted
- Kind: B2
- Application number: 18/182,848
- Filed: 2023-03-13
- Published: 2023-08-03
- Granted: 2025-02-04
- Earliest claimed: 2021-12-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Wilson Pradeep; Sriraj Chellappan; Shruti Gupta
- Web page: https://patentgrep.com/patent/US12216160B2

## CPC

- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318552: {Clock circuits details}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

## Claims

### Claim 1

An integrated circuit, comprising:
a clock shaper circuit, comprising:
a synchronizing circuit configured to provide a synchronizing signal based on a scan enable signal;
a clock leaker circuit coupled to the synchronizing circuit configured to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and
selection circuitry coupled to the clock leaker circuit configured to receive the second clock signal and select between a shift clock and the second clock signal based on the synchronizing signal.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the clock leaker circuit is configured to receive clock pulse configuration vectors based on the synchronizing signal and to provide the second clock signal based on the first clock signal.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the clock leaker circuit comprises a first set of multiplexers coupled to provide the clock pulse configuration vectors to a set of shift registers based on the shift clock.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the set of pulses are at a frequency greater than a frequency of the shift clock.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the selection circuitry comprises a multiplexer configured to:
receive the scan enable signal;
receive a one-cycle delay scan enable signal from a first shift register of the synchronizing circuit; and
provide a synchronizing scan enable signal based on the one-cycle delay scan enable signal.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, further comprising an integrated clock generator (ICG) circuit configured to provide the first clock signal based on the synchronizing signal.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further comprising a first inverter to provide an enable signal to the ICG circuit based on the synchronizing signal.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the selection circuitry comprises an AND gate configured to receive the second clock signal, a one-cycle delay scan enable signal, and a transition fault test enable signal, and to provide the second clock signal.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, further comprising a shaping integrated clock generator (ICG) circuit coupled to a multiplexer that includes a first input coupled to receive a third clock signal, a second input coupled to receive the second clock signal, and an output coupled to provide an output clock signal.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the third clock signal is at a frequency greater than a frequency of the shift clock.

### Claim 11

A method implemented by an integrated circuit, comprising:
receiving a set of data vectors at a clock shaper circuit;
receiving a first state of a scan enable signal at the clock shaper circuit,
receiving a second state of the scan enable signal at the clock shaper circuit, wherein the second state is opposite the first state; and
responsive to receiving the second state of the scan enable signal, applying an enable signal to a first integrated clock generator (ICG) circuit, wherein applying the enable signal comprises causing the clock shaper circuit to provide a set of clock pulses.

### Claim 12 (depends on 11)

The method of claim 11, wherein receiving the first state of the scan enable signal comprises:
applying the first state of the scan enable signal to a first shift register;
applying a set of clock pulses to a second shift register;
providing an output signal at an output node of the first shift register; and
loading the set of data vectors into a third shift register based on an inversion of the output signal.

### Claim 13 (depends on 11)

The method of claim 11, wherein receiving the second state of the scan enable signal comprises:
providing a first output signal from a first shift register as a gating signal for a set of multiplexers coupled to a third shift register;
providing an inversion of a second output signal from a second shift register to a second ICG circuit;
applying a shifted clock signal from the second ICG circuit to the third shift register; and
serially shifting the set of data vectors from the third shift registers to an adjacent shift register.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
receiving, by the clock shaper circuit, clock pulse configuration vectors based on a synchronizing signal; and
providing, by the clock shaper circuit, a second clock signal based on a first clock signal.

### Claim 15 (depends on 14)

The method of claim 14, further comprising providing, by the clock shaper circuit, the clock pulse configuration vectors to the clock shaper circuit based on a shift clock.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
receiving, by a selection circuit of the clock shaper circuit, the scan enable signal and a one-cycle delay scan enable signal; and
providing, by the selection circuit of the clock shaper circuit, a synchronizing scan enable signal based on the one-cycle delay scan enable signal.

### Claim 17 (depends on 11)

The method of claim 11, further comprising providing, by a second ICG circuit, a first clock signal based on a synchronizing signal.

### Claim 18 (depends on 11)

The method of claim 11, further comprising:
receiving, by a selection circuit of the clock shaper circuit, a clock signal, a one-cycle delay scan enable signal, and a transition fault test enable signal; and
providing, by the selection circuit of the clock shaper circuit, the clock signal.

### Claim 19 (depends on 11)

The method of claim 11, further comprising
receiving, by the first ICG circuit, a first clock signal at a first input of the first ICG and a clock signal at a second input of the first ICG; and
providing, by the first ICG, an output clock signal at an output of the first ICG circuit.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first clock signal is at a frequency greater than a frequency of a shift clock.