# US 12,216,159 B2 · Circuit and method to measure simulation to silicon timing correlation

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- Number: US 12,216,159 B2
- Document ID: US12216159B2
- Status: Granted
- Kind: B2
- Application number: 18/510,835
- Filed: 2023-11-16
- Published: 2024-03-14
- Granted: 2025-02-04
- Earliest claimed: 2020-12-01
- Assignees: MediaTek Singapore Pte. Ltd.
- Applicants: MediaTek Singapore Pte. Ltd.
- Inventors: Ashish Kumar Nayak; Hugh Thomas Mair; Anshul Varma; Anand Rajagopalan
- Web page: https://patentgrep.com/patent/US12216159B2

## CPC

- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- H03K 5/131: Digitally controlled
- G01R 31/2882: {Testing timing characteristics}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/3016: {Delay or race condition test, e.g. race hazard test}
- G01R 31/31937: {Timing aspects, e.g. measuring propagation delay (G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24)}
- H03K 3/0315: {Ring oscillators}
- H03K 5/134: with field-effect transistors
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

## Claims

### Claim 1

An integrated circuit, comprising:
a programmable ring oscillator comprising a delay path, the programmable ring oscillator being configured to propagate a first oscillator signal and a second oscillator signal along the delay path; and
a controller configured to determine a central tendency of propagation delay of the programmable ring oscillator using the first and second oscillator signals,
wherein the delay path comprises a plurality of oscillator stages, oscillator stages of the plurality of oscillator stages being switchable into and out of the delay path based on a plurality of respective control signals, the controller further configured to:
provide the plurality of control signals to the programmable ring oscillator;
obtain the first oscillator signal and the second oscillator signal from the programmable ring oscillator; and
determine first and second pulse widths of the first and second oscillator signals.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of oscillator stages comprises a first oscillator stage configured to receive a first control signal of the plurality of control signals, and wherein the programmable ring oscillator is configured to propagate the first oscillator signal through the first oscillator stage when the first control signal has a first state and bypass the first oscillator stage with the first oscillator signal when the first control signal has a second state.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the controller is configured to thermometer-encode the plurality of control signals.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the controller is configured to:
provide a first plurality of control signals to the programmable ring oscillator;
obtain the first oscillator signal from the programmable ring oscillator, the first oscillator signal being propagated along the delay path of the programmable ring oscillator in response to receiving the first plurality of control signals;
provide a second plurality of control signals to the programmable ring oscillator that is different from the first plurality of control signals;
obtain the second oscillator signal from the programmable ring oscillator, the second oscillator signal being propagated along the delay path of the programmable ring oscillator in response to receiving the second plurality of control signals; and
determine the central tendency of propagation delay using the first and second oscillator signals.

### Claim 5

An integrated circuit, comprising:
a first circuit, comprising:
a programmable ring oscillator comprising a first programmable delay path, the programmable ring oscillator being configured to propagate a first oscillator signal and a second oscillator signal along the first programmable delay path; and
a controller configured to determine a central tendency of propagation delay of the programmable ring oscillator using the first and second oscillator signals,
wherein the first programmable delay path comprises a plurality of oscillator stages, oscillator stages of the plurality of oscillator stages being switchable into and out of the first programmable delay path based on a first plurality of respective control signals; and
a second circuit, comprising:
a second programmable delay path comprising a plurality of path delay tuners configured to:
receive a second plurality of control signals; and
add to the second programmable delay path an amount of cell delay and an amount of wire delay that are based on the second plurality of control signals; and
a controller configured to provide the second plurality of control signals to the programmable delay path, receive a signal from the second programmable delay path, and compare the signal to a reference signal.