# US 12,216,157 B2 · Package structure and testing method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,216,157 B2
- Document ID: US12216157B2
- Status: Granted
- Kind: B2
- Application number: 18/236,930
- Filed: 2023-08-22
- Published: 2023-12-07
- Granted: 2025-02-04
- Earliest claimed: 2020-03-06
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Chen-Chao Wang; Tsung-Tang Tsai; Chih-Yi Huang
- Web page: https://patentgrep.com/patent/US12216157B2

## CPC

- G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)}
- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

## Claims

### Claim 1

A package structure, comprising:
a wiring structure including at least one conductive circuit layer and a test circuit structure disposed adjacent to an interconnection portion of the at least one conductive circuit layer;
a first electronic device electrically connected to the wiring structure; and
a second electronic device electrically connected to the wiring structure,
wherein the test circuit structure is not electrically connected to the interconnection portion of the at least one conductive circuit layer.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the test circuit structure includes a segment extending along the interconnection portion.

### Claim 3 (depends on 2)

The package structure of claim 2, wherein the segment is non-perpendicular to a conductive trace of the interconnection portion from a top view.

### Claim 4 (depends on 3)

The package structure of claim 3, wherein the segment is substantially parallel with the conductive trace of the interconnection portion from the top view.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein the test circuit structure includes a first segment disposed at a first side of the interconnection portion and a second segment disposed at a second side of the interconnection portion opposite to the first side.

### Claim 6 (depends on 5)

The package structure of claim 5, wherein the first segment is electrically connected to the second segment.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the interconnection portion and the test circuit structure are disposed at a same layer of the wiring structure.

### Claim 8 (depends on 5)

The package structure of claim 5, further comprising a connection portion connecting the first segment and the second segment, wherein the interconnection portion is disposed at a first layer of the wiring structure, and the connection portion is disposed at a second layer different from the first layer of the wiring structure.

### Claim 9 (depends on 1)

The package structure of claim 1, wherein a line width of a segment of the test circuit structure is substantially equal to a line width of a conductive trace of the interconnection portion.

### Claim 10 (depends on 1)

The package structure of claim 1, wherein the test circuit structure includes a plurality of segments, the interconnection portion includes a plurality of conductive traces, and a line space of the plurality of segments is substantially equal to a line space of the plurality of conductive traces.

### Claim 11

A package structure, comprising:
a wiring structure including a conductive circuit layer, wherein the conductive circuit layer includes a test circuit structure;
a first electronic device disposed over the wiring structure; and
a second electronic device disposed over the wiring structure, wherein the test circuit structure is not electrically connected to the first electronic device and the second electronic device.

### Claim 12 (depends on 11)

The package structure of claim 11, wherein in a top view, the test circuit structure is overlapped with the first electronic device or the second electronic device.

### Claim 13 (depends on 12)

The package structure of claim 12, wherein in the top view, the test circuit structure is overlapped with a gap between the first electronic device and the second electronic device.

### Claim 14 (depends on 13)

The package structure of claim 13, further comprising an underfill overlapped with the gap.

### Claim 15 (depends on 11)

The package structure of claim 11, wherein the wiring structure further includes an interconnection portion electrically connecting the first electronic device and the second electronic device, wherein in a top view, the interconnection portion is outflanked by the test circuit structure.

### Claim 16

A package structure, comprising:
a wiring structure having a first surface and a second surface opposite to the first surface, and including a conductive circuit layer and a test circuit structure disposed adjacent to the conductive circuit layer, wherein the test circuit structure is closer to the first surface than to the second surface, wherein the wiring structure further includes an exposed test via pad exposed from the second surface and electrically connected to the test circuit structure.

### Claim 17 (depends on 16)

The package structure of claim 16, further comprising an electronic device disposed over the first surface of the wiring structure.

### Claim 18 (depends on 17)

The package structure of claim 17, wherein in a top view, the test circuit structure extends from a region under a projection of the electronic device to outside of the projection of the electronic device.

### Claim 19 (depends on 16)

The package structure of claim 16, further comprising a re-flowable material attached to the wiring structure.

### Claim 20 (depends on 16)

The package structure of claim 16, further comprising a protection material disposed more adjacent to the test circuit structure than to the exposed test via pad.