# US 12,213,651 B2 · Imaging system and endoscope

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- Number: US 12,213,651 B2
- Document ID: US12213651B2
- Status: Granted
- Kind: B2
- Application number: 17/852,503
- Filed: 2022-06-29
- Published: 2022-10-13
- Granted: 2025-02-04
- Earliest claimed: 2020-01-09
- Assignees: Olympus Corporation
- Applicants: Olympus Corporation
- Inventors: Yasunari Harada
- Web page: https://patentgrep.com/patent/US12213651B2

## CPC

- A61B 1/045: Control thereof
- H04N 5/04: Synchronising (for television systems using pulse code modulation H04N7/56)
- A61B 1/00006: {of control signals}
- A61B 1/00018: {using electrical cables}
- H04N 7/18: Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
- H04N 23/555: {for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes}
- H04N 23/60: Control of cameras or camera modules
- H04N 23/665: {involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals}
- H04N 25/7795: {Circuitry for generating timing or clock signals}
- A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

In an imaging system, a video output circuit is configured to convert an analog video signal into digital data and output serial data including the digital data to a signal line on the basis of a serial clock having a higher frequency than a frequency of the camera clock. A camera-clock generation circuit is configured to generate the camera clock synchronized with the system clock output to the signal line. A serial-clock generation circuit is configured to generate the serial clock synchronized with the system clock output to the signal line. A system-clock output circuit is configured to output the system clock to the signal line in a blanking period.

## Claims

### Claim 1

An imaging system, comprising:
a camera unit; and
a control unit that is configured to operate on the basis of a system clock and is connected to the camera unit by a signal line that transmits serial data and the system clock,
wherein the camera unit comprises:
an imager configured to generate an analog video signal on the basis of a camera clock;
a video output circuit configured to convert the analog video signal into digital data and output the serial data including the digital data to the signal line on the basis of a serial clock having a higher frequency than a frequency of the camera clock;
a camera-clock generation circuit configured to generate the camera clock synchronized with the system clock output to the signal line; and
a serial-clock generation circuit configured to generate the serial clock synchronized with the system clock output to the signal line, and
the control unit comprises:
a video reception circuit that is electrically connected to the signal line and is configured to receive the serial data; and
a system-clock output circuit configured to output the system clock to the signal line in a blanking period during which output of the serial data to the signal line is stopped.

### Claim 2 (depends on 1)

The imaging system according to claim 1,
wherein the video output circuit comprises:
an analog-to-digital conversion circuit configured to convert the analog video signal into the digital data including a plurality of parallel bits; and
a serializer that is configured to convert the digital data into the serial data and output the serial data to the signal line at a timing synchronized with the serial clock.

### Claim 3 (depends on 1)

The imaging system according to claim 1,
wherein the video output circuit comprises an analog-to-digital conversion circuit that is configured to convert the analog video signal into the serial data and output the serial data to the signal line at a timing synchronized with the serial clock.

### Claim 4 (depends on 1)

The imaging system according to claim 1,
wherein the camera-clock generation circuit is configured to generate the camera clock by dividing a frequency of the serial clock.

### Claim 5 (depends on 1)

The imaging system according to claim 1,
wherein the serial data include two or more pieces of high level data and two or more pieces of low level data, and
the video output circuit comprises an encoding circuit configured to encode the serial data such that a sum of lengths of periods occupied by the two or more pieces of high level data output to the signal line is almost the same as a sum of lengths of periods occupied by the two or more pieces of low level data output to the signal line.

### Claim 6 (depends on 1)

The imaging system according to claim 1,
wherein the video output circuit comprises a three-state buffer configured to turn into any one of a high-level state, a low-level state, and a high-impedance state,
a state of the three-state buffer switches between the high-level state, the low-level state, and the high-impedance state, and
the three-state buffer is configured to output the serial data to the signal line by turning into the high-level state or the low-level state and turn into the high-impedance state in the blanking period.

### Claim 7 (depends on 1)

The imaging system according to claim 1,
wherein the system-clock output circuit is configured to output the system clock including a negative voltage to the signal line, and
the camera unit further comprises a capacitor that is configured to hold the negative voltage and output the negative voltage to the imager.

### Claim 8 (depends on 7)

The imaging system according to claim 7,
wherein the system-clock output circuit is configured to output the system clock alternately including a positive voltage and the negative voltage to the signal line, and
the camera unit further comprises:
a switch that is capable of switching between an ON state and an OFF state and is electrically connected to the signal line and the capacitor; and
a control circuit configured to set a state of the switch to the ON state when the negative voltage is output to the signal line and set the state of the switch to the OFF state when the positive voltage is output to the signal line.

### Claim 9 (depends on 7)

The imaging system according to claim 7,
wherein the system-clock output circuit is configured to output the system clock including the negative voltage lower than a design voltage designed for the imager such that the negative voltage input to the capacitor almost matches the design voltage.

### Claim 10

An endoscope connected to a control unit by a signal line that transmits serial data and a system clock, the endoscope comprising:
an imager configured to generate an analog video signal on the basis of a camera clock;
a video output circuit configured to convert the analog video signal into digital data and output the serial data including the digital data to the signal line on the basis of a serial clock having a higher frequency than a frequency of the camera clock;
a camera-clock generation circuit configured to generate the camera clock synchronized with the system clock output to the signal line in a blanking period during which output of the serial data to the signal line is stopped; and
a serial-clock generation circuit configured to generate the serial clock synchronized with the system clock output to the signal line.