Memory device having 2-transistor vertical memory cell and conductive shield structure

An apparatus comprising:

• a first memory cell including a first transistor and a second transistor, the first transistor including a first channel region and a first charge storage structure separated from the first channel region, and the second transistor including a second channel region formed over the charge storage structure;
• a second memory cell adjacent the first memory cell, the second memory cell including a third transistor and a fourth transistor, the third transistor including a third channel region and a second charge storage structure separated from the third channel region, and the fourth transistor including a fourth channel region formed over the second charge storage structure;
• a first access line adjacent a side of the first memory cell;
• a second access line adjacent a side of the second memory cell;
• a first dielectric material adjacent the first channel region;
• a second dielectric material adjacent the third channel region;
• and
• a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials, wherein:
• each of the first and second access lines and the conductive structure has a height in a direction perpendicular to a direction from the first memory cell to the second memory cell;
• and
• the height of the conductive structure is unequal to the height of each of the first and second access lines.

An apparatus comprising:

• a first trench, a second trench, and a third trench, the second trench being between the first and third trenches;
• a first memory cell between the first and second trenches, the first memory cell including a first side and a second side opposite from the first side, a first transistor including a first channel region and a first charge storage structure separated from the first channel region, and a second transistor including a second channel region formed over the charge storage structure;
• a second memory cell between the second and third trenches, the second memory cell including a first side and a second side opposite from the first side, a third transistor including a third channel region and a second charge storage structure separated from the third channel region, and a fourth transistor including a fourth channel region formed over the second charge storage structure;
• a first access line in the second trench and adjacent the second side of the first memory cell;
• a second access line in the second trench and adjacent the first side of the second memory cell;
• a first conductive shield structure adjacent the first side of the first memory cell, wherein the first conductive shield is electrically separated from the first access line;
• and
• a second conductive shield structure adjacent the second side of the second memory cell, wherein the second conductive shield is electrically separated from the second access line.

An apparatus comprising:

• a first trench, a second trench, and a third trench, the second trench being between the first and third trenches;
• a first memory cell between the first and second trenches, the first memory cell including a first side and a second side opposite from the first side, a first transistor including a first channel region and a first charge storage structure separated from the first channel region, and a second transistor including a second channel region formed over the charge storage structure;
• a second memory cell between the second and third trenches, the second memory cell including a first side and a second side opposite from the first side, a third transistor including a third channel region and a second charge storage structure separated from the third channel region, and a fourth transistor including a fourth channel region formed over the second charge storage structure;
• a first access line in the second trench and adjacent the second side of the first memory cell;
• a second access line in the second trench and adjacent the first side of the second memory cell;
• a first conductive shield structure adjacent the first side of the first memory cell;
• and
• a second conductive shield structure adjacent the second side of the second memory cell, wherein:
• each of the first and second access lines and the conductive shield structure has a thickness in a direction parallel to a direction from the first memory cell to the second memory cell;
• and
• the thickness of the conductive shield structure is greater than the thickness of each of the first and second access lines.

An apparatus comprising:

• a first trench, a second trench, and a third trench, the second trench being between the first and third trenches;
• a first memory cell between the first and second trenches, the first memory cell including a first side and a second side opposite from the first side, a first transistor including a first channel region and a first charge storage structure separated from the first channel region, and a second transistor including a second channel region formed over the charge storage structure;
• a second memory cell between the second and third trenches, the second memory cell including a first side and a second side opposite from the first side, a third transistor including a third channel region and a second charge storage structure separated from the third channel region, and a fourth transistor including a fourth channel region formed over the second charge storage structure;
• a first access line in the second trench and adjacent the second side of the first memory cell;
• a second access line in the second trench and adjacent the first side of the second memory cell;
• a first conductive shield structure adjacent the first side of the first memory cell;
• and
• a second conductive shield structure adjacent the second side of the second memory cell, wherein:
• each of the first and second access lines and the conductive shield structure has a height in a direction perpendicular to a direction from the first memory cell to the second memory cell;
• and
• the height of the conductive shield structure is greater than the height of each of the first and second access line.