Circuit, apparatus and method for calculating multiplicative inverse

A method for calculating a multiplicative inverse, the method being performed by an apparatus for calculating a multiplicative inverse, the method comprising:

• receiving input data;
• dividing an input degree-8 finite field corresponding to the input data into two first degree-4 finite fields so as to perform Advanced Encryption Standard (AES) encryption on the input data, and performing a multiplicative inverse calculation on the first degree-4 finite fields in consideration of a circuit depth value (T-Depth) and qubit consumption of quantum gates in a quantum circuit;
• and
• outputting result data obtained by performing the multiplicative inverse calculation,
• wherein performing the multiplicative inverse calculation is configured to perform a multiplication on the first degree-4 finite fields using three degree-2 multipliers that are configured in consideration of the circuit depth value (T-depth) and the qubit consumption of the quantum gates, thus obtaining a second degree-4 finite field,
• wherein the three degree-2 multipliers are configured such that a number, a type and an arrangement of quantum gates included in each of the degree-2 multipliers are determined based on a circuit depth value (T-depth) and qubit consumption of the quantum gates,
• wherein each of degree-2 multipliers comprises:
• a plurality of interconnected logic gates, configured to perform multiplication operations to produce the corresponding polynomial product.

A circuit for calculating a multiplicative inverse, comprising:

• a first degree-4 polynomial multiplication circuit configured to perform a multiplication on two first degree-4 finite fields, which are divided from a received input degree-8 finite field so as to perform Advanced Encryption Standard (AES) encryption on input data in a quantum computer environment, using three degree-2 polynomial multiplication circuits that are configured in consideration of a circuit depth value (T-Depth) and qubit consumption of quantum gates, thus obtaining a second degree-4 infinite field;
• a degree-4 polynomial inverse computation circuit electrically connected to the first degree-4 polynomial multiplication circuit and configured to perform a multiplication on two second degree-2 finite fields divided from the second degree-4 finite field using the three second-degree polynomial multiplication circuits, thus calculating a multiplicative inverse of the second degree-2 finite fields;
• a second degree-4 polynomial multiplication circuit electrically connected to the degree-4 polynomial inverse computation circuit and configured to perform a multiplication on any one of the first degree-4 finite fields and the multiplicative inverse of the second degree-2 finite fields using the three degree-2 polynomial multiplication circuits, thus obtaining a third degree-4 finite field;
• and
• a third degree-4 polynomial multiplication circuit electrically connected to the degree-4 polynomial inverse computation circuit and configured to perform a multiplication on a remaining one of the first degree-4 finite fields and the multiplicative inverse of the second degree-2 finite fields using the three degree-2 polynomial multiplication circuits, thus obtaining a fourth degree-4 finite field,
• wherein the three degree-2 polynomial multiplication circuits are configured such that a number, a type and an arrangement of quantum gates included in each of the degree-2 polynomial multiplication circuits are determined based on a circuit depth value (T-depth) and qubit consumption of the quantum gates
• wherein each of the degree-4 polynomial multiplication circuits, each of the degree-2 polynomial multiplication circuits and the degree-4 polynomial inverse computation circuit comprises:
• a plurality of interconnected logic gates, configured to perform multiplication operations to produce the corresponding polynomial product.