Circuit for SAR ADC

A circuit, comprising:

• a positive-terminal p-type transistor;
• a negative-terminal p-type transistor;
• a positive-terminal n-type transistor, wherein the positive-terminal p-type transistor and the positive-terminal n-type transistor are cascoded between first reference voltage and second reference voltage, a drain of the positive-terminal n-type transistor is coupled to a drain of the positive-terminal p-type transistor and outputs a positive-terminal output signal;
• a negative-terminal n-type transistor, wherein the negative-terminal p-type transistor and the negative-terminal n-type transistor are cascoded between the first reference voltage and the second reference voltage, a drain of the negative-terminal n-type transistor is coupled to a drain of the negative-terminal p-type transistor and outputs a negative-terminal output signal;
• a first positive-terminal capacitor, wherein a top plate of the first positive-terminal capacitor is coupled to a gate of the positive-terminal n-type transistor;
• a first negative-terminal capacitor, wherein a top plate of the first negative-terminal capacitor is coupled to a gate of the negative-terminal n-type transistor;
• and
• a first control circuit, configured to generate a first control signal according to the positive-terminal output signal, the negative-terminal output signal and the target common mode voltage, wherein the first control signal is selectively coupled to the top plate of the first positive-terminal capacitor and the top plate of the first negative-terminal capacitor;
• wherein a positive-terminal input signal of an amplifier is selectively coupled to a bottom plate of the first positive-terminal capacitor, and a negative-terminal input signal of the amplifier is selectively coupled to a bottom plate of the first negative-terminal capacitor.