Phase detectors with extrapolation of timing events

A digital phase-locked loop (DPLL) comprising:

• a first timing detector configured to generate a first plurality of digital representations of timing of a first clock signal, wherein the first plurality of digital representations includes a first digital representation of a first timing event and a second digital representation of a second timing event;
• a second timing detector configured to generate a second plurality of digital representations of timing of a second clock signal;
• and
• a phase detector configured to provide phase detection based on the first plurality of digital representations and the second plurality of digital representations, wherein the phase detector is configured to generate a first extrapolated timing event based on adjusting the second digital representation by a time interval between the second timing event and the first timing event, wherein the phase detector is configured to provide phase detection based on the first extrapolated timing event,
• wherein the first plurality of digital representations includes a third digital representation of a third timing event, wherein the phase detector is further configured to generate a second extrapolated timing event based on adjusting the digital representation of the third timing event by a time interval between the third timing event and the first timing event.

A method of phase detection in a digital phase-locked loop (DPLL), the method comprising:

• generating a digital representation of a first timing event of an input clock signal to a phase detector;
• generating a digital representation of a second timing event of the input clock signal;
• extrapolating a first extrapolated timing event based on adjusting the digital representation of the second timing event by a time interval between the second timing event and the first timing event;
• and
• providing phase detection using the first extrapolated timing event, wherein the first timing event corresponds to an edge associated with a carrier frequency of the input clock signal, and the second timing event corresponds to an edge associated with a sub-carrier frequency of the input clock signal.