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AssigneeMicrosoft Technology Licensing, LLC
InventorsPing Lu, Bupesh Pandita, Minhan Chen
Estimating the term…
In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.
A calibrated phase-locked loop (PLL), comprising:
A method of operating a calibrated digital phase-locked loop (PLL), comprising:
An integrated circuit, comprising:
Dependencies are inferred from the claim text.