Low power quadrature phase detector
AssigneeMediatek Inc.
InventorsFong-Wen Lee, Wen-Chieh Wang, Yu-Hsin Lin
Life of this patent
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Abstract
The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
Claims20
A quadrature phase detector, comprising:
- a first detection circuit configured to detect a phase difference between a first clock signal and a second clock signal, comprising:
- a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
- a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a ground voltage, wherein the second switch and the first switch are controlled by the second clock signal with a same phase;
- and
- a first filter, configured to filter voltages at the first node to generate a first detection result, wherein the first detection result indicates the phase difference between the first clock signal and the second clock signal.
A quadrature phase detector, comprising:
- a first detection circuit configured to detect a phase difference between a first clock signal and a second clock signal, comprising:
- a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
- a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a reference voltage;
- and
- a first filter, configured to filter voltages at the first node to generate a first detection result;
- wherein ideally a phase difference between the first clock signal and the second clock signal is equal to 90 degrees, and the quadrature phase detector further comprises:
- a second detection circuit, comprising:
- a third switch, wherein the third switch is controlled by a third clock signal to selectively couple the second clock signal to a second node;
- a fourth switch, wherein the fourth switch is controlled by the third clock signal to selectively coupled the second node to the reference voltage;
- and
- a second filter, configured to filter voltages at the second node to generate a second detection result.
A circuitry, comprising:
- a clock signal generator, configured to generate a first clock signal and a second clock signal,
- a first detection circuit configured to detect a phase difference between the first clock signal and the second clock signal, comprising:
- a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
- a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a ground voltage, wherein the second switch and the first switch are controlled by the second clock signal with a same phase;
- and
- a first filter, configured to filter voltages at the first node to generate a first detection result, wherein the first detection result indicates the phase difference between the first clock signal and the second clock signal;
- a control circuit, coupled to the first detection circuit, configured to generate a control signal to adjust a phase of the first clock signal or the second clock signal according to the first detection result.
A circuitry, comprising:
- a clock signal generator, configured to generate a first clock signal and a second clock signal,
- a first detection circuit configured to detect a phase difference between the first clock signal and the second clock signal, comprising:
- a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
- a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a reference voltage;
- and
- a first filter, configured to filter voltages at the first node to generate a first detection result;
- a control circuit, coupled to the first detection circuit, configured to generate a control signal to adjust a phase of the first clock signal or the second clock signal according to the first detection result;
- wherein ideally a phase difference between the first clock signal and the second clock signal is equal to 90 degrees, and the quadrature phase detector further comprises:
- a second detection circuit, comprising:
- a third switch, wherein the third switch is controlled by a third clock signal to selectively couple the second clock signal to a second node;
- a fourth switch, wherein the fourth switch is controlled by the third clock signal to selectively coupled the second node to the reference voltage;
- and
- a second filter, configured to filter voltages at the second node to generate a second detection result.
Dependencies are inferred from the claim text.