Method for eliminating divot formation and semiconductor device manufactured using the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Wen Tseng, Po-Wei Liu, Hung-Ling Shih, Tsung-Yu Yang, Tsung-Hua Yang, Yu-Chun Chang
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Abstract
A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
Claims20
A method for eliminating divot formation, comprising:
- forming an isolation layer;
- forming a conduction layer which has a boundary with the isolation layer;
- etching back the isolation layer;
- and
- etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
A method for manufacturing a semiconductor device, comprising:
- forming a shallow trench isolation (STI) structure located at a first substrate portion of a semiconductor substrate;
- forming a deep trench isolation (DTI) structure which is located in the STI structure and which extends through a second substrate portion of the semiconductor substrate, the second substrate portion being located beneath the first substrate portion, the DTI structure including a conduction layer and an isolation layer disposed to separate the conduction layer from the first and second substrate portions, the conduction layer having a boundary with the isolation layer;
- etching back the isolation layer;
- and
- etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
A method for manufacturing a semiconductor device, comprising:
- forming a shallow trench isolation (STI) structure located at a first substrate portion of a semiconductor substrate;
- forming a deep trench isolation (DTI) structure which extends through the STI structure in the first substrate portion and extends through a second substrate portion of the semiconductor substrate, the second substrate portion being located beneath the first substrate portion, the DTI structure including a conduction layer and an isolation layer disposed to separate the conduction layer from the STI structure, the first substrate portion and the second substrate portion, the conduction layer having a boundary with the isolation layer;
- etching back the isolation layer;
- and
- etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
Dependencies are inferred from the claim text.