Cell architecture with extended transistor geometry

An integrated circuit (IC), comprising:

• first, second and third power rails located over a semiconductor substrate and having a respective first, second and third centerlines, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity;
• a plurality of first logic cells arranged over the semiconductor substrate in first and second rows, the first centerline located between the first row and the second row, each of the plurality of first logic cells including and a corresponding semiconductor structure comprising at least one transistor and interconnections that implement a respective logic function, and
• for each first logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and
• for each first logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines;
• and
• an extension logic cell arranged over the semiconductor substrate in the first row and including an extended semiconductor structure comprising at least one transistor with a source region and a drain region and interconnections, the extended semiconductor structure configured to implement at least a logic function, a portion of the source region or the drain region crossing the first centerline into the second row.