Selective removal of an etching stop layer for improving overlay shift tolerance

A device comprising:

• a first silicon oxide layer;
• a first metal interconnect structure disposed in the first silicon oxide layer;
• a metal silicon oxide layer that covers a top surface of the first silicon oxide layer, wherein at least a portion of a top surface of the first metal interconnect structure is not covered by the first metal silicon oxide layer;
• a metal oxide layer that covers a top surface of the metal silicon oxide layer and a first portion of the top surface of the first metal interconnect structure;
• a second silicon oxide layer disposed over the metal oxide layer;
• and
• a second metal interconnect structure disposed in the second silicon oxide layer and the metal oxide layer, wherein the second metal interconnect structure covers a second portion of the top surface of the first metal interconnect structure and a portion of the second silicon oxide layer is disposed between the metal oxide layer and a sidewall of the second metal interconnect structure.

A device comprising:

• a first dielectric layer of a multilayer interconnect;
• a first conductive feature of the multilayer interconnect, wherein the first conductive feature is disposed in the first dielectric layer and the first conductive feature has a first top and a first bottom opposite the first top;
• a second conductive feature of the multilayer interconnect, wherein the second conductive feature is disposed in the first dielectric layer, the second conductive feature has a second top, and the second conductive feature has a second bottom opposite the second top;
• a metal silicon oxide layer of the multilayer interconnect, wherein the metal silicon oxide layer has a first portion and a second portion disposed directly on the first dielectric layer, the second portion of the metal silicon oxide layer extends from a first edge of the first conductive feature to a second edge of the second conductive feature, and the first edge extends from the first top to the first bottom and the second edge extends from the second top to the second bottom;
• a metal oxide layer of the multilayer interconnect, wherein the metal oxide layer is disposed directly on the first portion and the second portion of the metal silicon oxide layer, the first top of the first conductive feature, and the second top of the second conductive feature;
• a second dielectric layer of the multilayer interconnect, wherein the second dielectric layer is disposed directly on the metal oxide layer;
• a third conductive feature of the multilayer interconnect, wherein the third conductive feature is disposed in the second dielectric layer and the third conductive feature is disposed directly on the first top of the first conductive feature;
• and
• wherein the first portion of the metal silicon oxide layer and the second portion of the metal silicon oxide layer are separated by a spacing, wherein the spacing overlaps the first top of the first conductive feature, and wherein at least the metal oxide layer, the third conductive feature, and the second dielectric layer fill the spacing.