User-configurable high-speed line driver

An adaptive line driver circuit configured to transmit a signal over a wired link, the adaptive line driver circuit comprising:

• a delay-locked loop circuit, providing sub unit interval (UI) user-configurable durations adapted to form pre-emphasis and feed-forward equalization of the signal by retiming the signal, the delay locked loop circuit providing a user-configurable quantity of pre-emphasis taps to retime the signal;
• a signal retiming circuit providing pre-emphasis data tap outputs comprising a main data signal referenced to delayed clock outputs from the delay-locked loop circuit;
• and
• a plurality of source-series terminated (SST) driver circuits, the source-series terminated (SST) driver circuits operatively coupled in groups to the signal re-timing circuit, a quantity of SST drivers in a group defining coefficients of pre-emphasis, groups of SST drivers operating in parallel with ganged outputs providing the signal to be transmitted.