Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorsToshio Hino, Junji Iwahori
Life of this patent
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Abstract
A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.
Claims19
A semiconductor integrated circuit device comprising
- a circuit block including a first cell row having a plurality of cells arranged in a first direction, wherein
- the first cell row includes:
- a first cell-row-terminating cell that does not contribute to a logical function of the circuit block disposed at a first end of the first cell row, and
- a first cell that is adjacent to the first cell-row terminating cell in the first direction;
- and
- the first cell-row-terminating cell includes:
- a first nanowire extending in the first direction in a first P-type transistor area,
- a first pad connected to the first nanowire,
- a second nanowire extending in the first direction in a first N-type transistor area,
- a second pad connected to the second nanowire, and
- a plurality of gate structures extending in a second direction perpendicular to the first direction, including a first gate structure placed at a cell end on an inner side of the circuit block, and a second gate structure adjacent to the first gate structure in the first direction;
- and
- the first cell includes:
- a third nanowire extending in the first direction in the first P-type transistor area,
- a third pad connected to the third nanowire and facing the first pad,
- a fourth nanowire extending in the first direction in the first N-type transistor area,
- a fourth pad connected to the fourth nanowire and facing the second pad,
- a third gate structure adjacent to the first gate structure in the first direction.
Dependencies are inferred from the claim text.