# US 12,205,657 B2 · Hybrid smart verify for QLC/TLC die

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- Number: US 12,205,657 B2
- Document ID: US12205657B2
- Status: Granted
- Kind: B2
- Application number: 17/895,412
- Filed: 2022-08-25
- Published: 2024-02-29
- Granted: 2025-01-21
- Earliest claimed: 2022-08-25
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Xiang Yang; Henry Chin; Erika Penzo; Muhammad Masuduzzaman
- Web page: https://patentgrep.com/patent/US12205657B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G11C 2211/5649: Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.

## Claims

### Claim 1

An apparatus comprising:
one or more control circuits configured to connect to a memory structure comprising non-volatile memory cells, wherein the one or more control circuits are configured to:
program a first group of the memory cells in the memory structure using a four-bit code having sixteen states and four pages;
program a second group of the memory cells in the memory structure using a three-bit code based on three pages of the four pages, wherein the three-bit code includes eight states of the sixteen states of the four-bit code for which an unused page of the four-bit code comprises a default value; and
begin to verify during programming using the three-bit code, for each particular state of a first set of one or more states of the eight states, during a program-verify loop determined based on whether a number of memory cells having a threshold voltage above a verify voltage for a state that immediately precedes the particular state in threshold voltage is greater than a pre-determined number.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are further configured to:
begin to verify during programming using the three-bit code, for each particular state of a second set of one or more states of the eight states, during a program-verify loop determined based on a pre-determined number of program-verify loops following beginning to verify a state that immediately precedes the particular state in threshold voltage.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein:
the eight states includes an erase state, and A-, B-, C-, D-, E-, F-, and G-states in increasing threshold voltages; and
the first set includes the B-state.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein:
the second set includes the C-, D-, E-, F-, and G-states.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the first set comprises:
all states in the three-bit code that immediately follow a state in the four-bit code that is also used in the three-bit code.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein:
the eight states includes an erase state, and A-, B-, C-, D-, E-, -F, and G-states in increasing threshold voltages; and
the first set includes the B-state whether the B-state follows a state in the four-bit code that is also used in the three-bit code or whether the B-state follows a state in the four-bit code that is not used in the three-bit code.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the second set comprises:
states in the three-bit code that immediately follow a state in the four-bit code that is not used in the three-bit code, but does not include any state in the four-bit code that is also used in the three-bit code.

### Claim 8 (depends on 1)

The apparatus of claim 1 wherein to program the second group of the memory cells in the memory structure using the three-bit code based on three of the four pages of the four-bit code includes the one or more control circuits being further configured to:
load three data pages into a corresponding three sets of data latches associated with memory cells; and
load the default value into a fourth set of data latches associated with memory cells, wherein the default value is the same for all data latches in the fourth set of data latches.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the one or more control circuits are further configured to:
program the three data pages into the memory cells based on a programming algorithm that considers the three data pages in the corresponding three sets of data latches and the default value in the fourth set of data latches.