Memory device and programming method thereof

A memory device, comprising:

• a memory array, comprising a plurality of multi-level cells;
• and
• a memory controller, coupled to the memory array, configured to:
• select a multi-level cell among the plurality of multi-level cells;
• apply a sequence of program pulses comprising at least one set pulse and at least one reset pulse to the multi-level cell, wherein the at least one set pulse is configured to reduce a resistance of the multi-level cell, and the at least one reset pulse is configured to increase the resistance of the multi-level cell;
• determine whether the resistance of the multi-level cell is in a target range after each program pulse of the sequence of program pulses is applied to the multi-level cell;
• keep applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is not in the target range;
• and
• stop applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is in the target range,
• wherein the at least one set pulse comprises incremental step set pulses, and the at least one reset pulse comprises a series of incremental step reset pulses.

A programming method of a memory device comprising a multi-level cell, the programming method comprising:

• applying a sequence of program pulses comprising at least one set pulse and at least one reset pulse to the multi-level cell, wherein the at least one set pulse is configured to decrease a resistance of the multi-level cell, and the at least one reset pulse is configured to increase the resistance of the multi-level cell;
• determining whether the resistance of the multi-level cell is in a target range after each program pulse of the sequence of program pulses is applied to the multi-level cell;
• keeping applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is not in the target range;
• and
• stopping applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is in the target range,
• wherein applying the sequence of program pulses comprising the at least one set pulse and the at least one reset pulse to the multi-level cell comprises:
• successively applying at least one first program pulse to a first electrode of the multi-level cell or to a control terminal of a transistor of the multi-level cell until the resistance of the multi-level cell is in the target range or until the resistance of the multi-level cell passes a first limit of the target range;
• determining at least one second program pulse to be applied to a second electrode of the multi-level cell in response to determining that the resistance of the multi-level cell passes the first limit of the target range;
• and
• successively applying the at least one second program pulse to the second electrode of the multi-level memory cell or to the control terminal of the transistor of the multi-level cell until the resistance of the multi-level cell is in the target range or until the resistance of the multi-level cell goes beyond a second limit of the target range.