Communication logic to enhance area effectiveness for memory repair mechanism

A method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP), the method comprising:

• asserting, by an OTP sequencer circuit, a first grant signal;
• a first loading, by a first main-controller, of a first repair data for a first sub-set of the local memory associated with the first main-controller from a first partition of the OTP memory;
• communicating, by the first main-controller, a first status signal to the OTP sequencer circuit after completion of the first loading indicating a completion of the first loading;
• de-asserting, by the OTP sequencer circuit, the first grant signal in response to the OTP sequencer circuit receiving the first status signal;
• asserting, by the OTP sequencer circuit, a second grant signal in response to the de-asserting of the first grant signal;
• adding, by an offset addition and selection logic circuit, an offset to an address used by a second main-controller to access a second partition of the OTP memory comprising a second repair data, wherein the first repair data and the second repair data are sequentially loaded in the OTP memory;
• a second loading, by the second main-controller, of the second repair data for a second sub-set of the local memory associated with the second main-controller from the second partition of the OTP memory using the address to access the second partition;
• communicating, by the second main-controller, a second status signal to the OTP sequencer circuit after completion of the second loading indicating a completion of the second loading;
• and
• de-asserting, by the OTP sequencer circuit, the second grant signal in response to the OTP sequencer circuit receiving the second status signal.

A system for testing and repairing local memory in a hardware accelerator, the system comprising:

• a one-time programmable (OTP) memory configured to sequentially store first repair data in a first partition and second repair data in a second partition for, respectively, a first subset of the local memory and a second subset of the local memory;
• a test control register (TCR) configured to assert a first grant signal;
• a first main-controller coupled to the first subset of the local memory, the first main-controller configured to first load the first repair data for the first subset of the local memory from the first partition in response to the first grant signal being asserted;
• an offset addition and selection logic circuit coupled to the TCR and the first main-controller, the offset addition and selection logic circuit configured to add an offset to an address used by a second main-controller to access the second partition, wherein the TCR is further configured to de-assert the first grant signal and assert a second grant signal in response to the de-asserting of the first grant signal;
• and
• the second main-controller configured to second load the second repair data for the second subset of the local memory associated with the second main-controller from the second partition using the address to access the second partition in response to the second grant signal being asserted, wherein the TCR is further configured to de-assert the second grant signal.